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ACE24AC02A3FMTH Scheda tecnica(PDF) 6 Page - ACE Technology Co., LTD. |
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ACE24AC02A3FMTH Scheda tecnica(HTML) 6 Page - ACE Technology Co., LTD. |
6 / 17 page ACE24AC02A3 Two-wire Serial EEPROM VER 1.3 6 words are loaded, the 17 th data word will be loaded to the 1 st data word column address. The 18 th data word will be loaded to the 2 nd data word column address and so on. In other word, data word address (column address) will “roll” over the previously loaded data. C. Acknowledge Polling Acknowledge polling may be used to poll the programming status during a self-timed internal programming. By issuing a valid read or write address command, the EEPROM will not acknowledge at the 9 th clock cycle if the device is still in the self-timed programming mode. However, if the programming completes and the chip has returned to the standby mode, the device will return a valid acknowledge signal at the 9 th clock cycle. Read Operations The read command is similar to the write command except the 8 th read/write bit in address word is set to “1”. The three read operation modes are described as follows: (A) Current Address Read The EEPROM internal address word counter maintains the last read or write address plus one if the power supply to the device has not been cut off. To initiate a current address read operation, the micro-controller issues a start bit and a valid device address word with the read/write bit (8 th ) set to “1”. The EEPROM will response with an acknowledge signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out. The internal address word counter will then automatically increase by one. For current address read the micro-controller will not issue an acknowledge signal on the 18 th clock cycle. The micro-controller issues a valid stop bit after the 18 th clock cycle to terminate the read operation. The device then returns to standby mode. (B) Sequential Read The sequential read is very similar to current address read. The micro-controller issues a start bit and a valid device address word with read/write bit (8 th) set to “1”. The EEPROM will response with an acknowledge signal on the 9 th serial clock cycle. An 8-bit data word will then be serially clocked out. Meanwhile the internally address word counter will then automatically increase by one. Unlike current address read, the micro-controller sends an acknowledge signal on the 18 th clock cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the acknowledge signal, the EEPROM will serially clocked out an 8-bit data word based on the incremented internal address counter. If the micro-controller needs another data, it sends out an acknowledge signal on the 27 th clock cycle. Another 8-bit data word will then be serially clocked out. This sequential read continues as long as the micro-controller sends an acknowledge signal after receiving a new data word. When the internal address counter reaches its maximum valid address, it rolls over to the beginning of the memory array address. Similar to current address read, the micro-controller can terminate the sequential read by not acknowledging the last data word received, but sending a stop bit afterwards instead. |
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