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FAN5009MPX Scheda tecnica(PDF) 9 Page - Fairchild Semiconductor

Il numero della parte FAN5009MPX
Spiegazioni elettronici  Dual Bootstrapped 12V MOSFET Driver
Download  13 Pages
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Produttore elettronici  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FAN5009MPX Scheda tecnica(HTML) 9 Page - Fairchild Semiconductor

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PRODUCT SPECIFICATION
FAN5009
REV. 1.0.5 7/22/04
9
Thermal Considerations
Total device dissipation:
where PQ represents quiescent power dissipation:
where FSW is switching frequency (in kHz).
PR is power dissipated in the bootstrap rectifier:
Where QG1 is total gate charge of the upper FET (Q1) for
it’s applied VGS.
VF for the applied IF(AVG) can be graphically determined
using the datasheet curves, where:
PHDRV represents internal power dissipation of the upper
FET driver.
Where PH(R) and PH(F) are internal dissipations for the
rising and falling edges, respectively:
where:
As described in eq. 8 and 9 above, the total power consumed
in driving the gate is divided in proportion to the resistances
in series with the MOSFET's internal gate node as shown
below:
Figure 5. Driver dissipation model
RG is the polysilicon gate resistance, internal to the FET.
RE is the external gate drive resistor implemented in many
designs. Note that the introduction of RE can reduce driver
power dissipation, but excess RE may cause errors in the
“adaptive gate drive” circuitry. For more information please
refer to Fairchild app note AN-6003, “Shoot-through” in
Synchronous Buck Converters.
PLDRV is dissipation of the lower FET driver.
Where PH(R) and PH(F) are internal dissipations for the
rising and falling edges, respectively:
where:
Layout Considerations
Use the following general guidelines when designing printed
circuit boards (see Figures 6 and 7):
1.
Trace out the high-current paths and use short, wide
(>25 mil) traces to make these connections.
2.
Connect the PGND pin of the FAN5009 as close as
possible to the source of the lower MOSFET.
3.
The VCC bypass capacitor should be located as close as
possible to VCC and PGND pins.
4.
Use vias to other layers when possible to maximize
thermal conduction away from the IC.
Figure 6. External component placement
recommendation for SO8 package (not to scale)
P
D
P
Q
P
R
P
HDRV
P
LDRV
++
+
=
(3)
P
Q
V
CC
4mA + 0.036 F
SW
100
()
[]
×
=
(4)
P
R
V
F
F
SW
×
Q
G1
×
=
(5)
I
F AVG
()
F
SW
Q
G1
×
=
(6)
P
HDRV
P
HR
()
P
HF
()
+
=
(7)
P
HR
()
P
Q1
R
HUP
R
HUP
R
E
R
G
++
----------------------------------------
×
=
(8)
P
HF
()
P
Q1
R
HDN
R
HDN
R
E
R
G
++
-----------------------------------------
×
=
(9)
P
Q1
1
2
---
Q
×
G1
V
GS Q1
()
F
SW
×
×
=
(10)
HDRV
Q1
G
R
G
R
E
R
HUP
BOOT
SW
R
HDN
S
P
LDRV
P
LR
()
P
LF
()
+
=
(11)
P
LR
()
P
Q2
R
LUP
R
LUP
R
E
R
G
++
----------------------------------------
×
=
(12)
P
LF
()
P
Q2
R
LDN
R
HDN
R
E
R
G
++
-----------------------------------------
×
=
(13)
P
Q2
1
2
---
Q
×
G2
V
GS Q2
()
F
SW
×
×
=
(14)
1
2
3
4
8
7
6
5
C
BOOT
C
VCC


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