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AD8380JS Scheda tecnica(PDF) 3 Page - Analog Devices |
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AD8380JS Scheda tecnica(HTML) 3 Page - Analog Devices |
3 / 16 page REV. B –3– AD8380 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 NC No Connect. 2–11 DB[0:9] Video Data Inputs. DB9 is the MSB. 12 E/ O Even/Odd data select, input latches are loaded at the falling edge of CLK if E/ O is low or rising edge if E/ O is high. 13 R/ L Determines starting point of internally generated channel-loading sequence. R/ L Low (when address = 111) loads from Channel 0 up to Channel 5. 14 INV When high, analog video outputs are above the VMID setpoint. See Figure 3. 15, 16 DVEE, DVCC Digital Supplies. Nominally 3.3 V and 0 V, respectively. 17, 20, 22, 24, 26, 28, 30, 32, 34, 37, 38 AVCCxxx, AVEExxx Analog Supplies. Nominally 15 V and 0 V, respectively. 18 STBY Stand By. When high, all digital and analog circuits are “debiased” and the power dissipation drops to a minimum. 19 BYP An external capacitor connected from here to VEE will help to ensure rapid DAC settling time. 21 VMID Externally supplied voltage applied here sets the midpoint reference for the video output. 23, 25, 27, 29, 31, 33 VID5–VID0 Analog Video Outputs. 36, 35 VREFHI, VREFLO Voltage between these pins sets DAC full-scale range. An external reference must be applied and should be common to all devices to ensure best tracking. 39–41 A[0:2] 3-bit channel address for addressable loading of the digital input latches. 42 STSQ/CS STSQ to start internal sequencing or Chip Select to enable addressable channel addressing. See functional description. Used in conjunction with A[0:2]. 43 XFR If XFR = HIGH at the rising edge of CLK, data is transferred to the DACs on the next falling edge of CLK. See Figures 4, 6, 7, and 8. 44 CLK Master Clock Input. CHANNEL SELECTION FUNCTIONALITY There are two channel selection modes, addressed channel loading, (in which the user directly controls which DAC is loaded), and internally sequenced loading (in which the user controls the direction and clock phase in which the loading proceeds). ADDRESSED CHANNEL LOADING: When channel address (A0, A1, A2) = 000 through 101, the video data is loaded into Channels 0 through 5. (STSQ/CS functions as “Chip Selection” this case.) INTERNALLY SEQUENCED LOADING: When channel address = 111 the video data is loaded in a sequence determined internally. The sequencing is initiated by a pulse applied to STSQ/CS input. The count proceeds from 0 to 5 if R/ L is LOW or from 5 to 0 if R/L is HIGH. DAC TRANSFER FUNCTION VOUT = VMID + VFS × (1 – N/1023); if INV is HIGH, VOUT = VMID – VFS × (1 – N/1023); if INV is LOW where VFS = 2 × (VREFHI – VREFLO) MAXIMUM OUTPUT VOLTAGE The maximum output signal swing is constrained by the output voltage compliance of the DACs and the output dynamic range of the output amplifiers. The minimum voltage allowed at the outputs of the DACs is about 6 V. This constrains the minimum value of VMID to be 6 V. The output amplifiers will swing and settle cleanly, as described on the specification page, for output voltages within 1.5 V from each supply voltage rail. For a given value of VMID, the voltage required to saturate the video output voltages defines the maximum usable full-scale voltage. For example, if VMID is less than AVCC/2, the maxi- mum value of VFS is (VMID – 1.5 V). If VMID is greater than AVCC/2, the maximum useful VFS is (AVCC – 1.5 – VMID). Figure 1 graphically describes these limiting factors. 6 7.5 VMID – Volts 6 4.5 Figure 1. Valid Range for VMID with Respect to VFS (AVCC = 15 V) |
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