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MT9V032 Scheda tecnica(PDF) 49 Page - ON Semiconductor

Il numero della parte MT9V032
Spiegazioni elettronici  1/3?륤nch Wide VGA CMOS Digital Image Sensor
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Table 10.
LVDS PACKET FORMAT IN STEREOSCOPY MODE (Stereoscopy Mode Bit Asserted)
18−bit Packet
Function
Bit[0]
1’b1 (Start bit)
Bit[1]
Master Sensor Pixel Data [2]
Bit[2]
Master Sensor Pixel Data [3]
Bit[3]
Master Sensor Pixel Data [4]
Bit[4]
Master Sensor Pixel Data [5]
Bit[5]
Master Sensor Pixel Data [6]
Bit[6]
Master Sensor Pixel Data [7]
Bit[7]
Master Sensor Pixel Data [8]
Bit[8]
Master Sensor Pixel Data [9]
Bit[9]
Slave Sensor Pixel Data [2]
Bit[10]
Slave Sensor Pixel Data [3]
Bit[11]
Slave Sensor Pixel Data [4]
Bit[12]
Slave Sensor Pixel Data [5]
Bit[13]
Slave Sensor Pixel Data [6]
Bit[14]
Slave Sensor Pixel Data [7]
Bit[15]
Slave Sensor Pixel Data [8]
Bit[16]
Slave Sensor Pixel Data [9]
Bit[17]
1’b0 (Stop bit)
Control signals LINE_VALID and FRAME_VALID can
be reconstructed from their respective preceding and
succeeding flags that are always embedded within the pixel
data in the form of reserved words.
Table 11.
RESERVED WORDS IN THE PIXEL DATA STREAM
Pixel Data Reserved Word
Flag
0
Precedes frame valid assertion
1
Precedes line valid assertion
2
Succeeds line valid de−assertion
3
Succeeds frame valid de−assertion
When LVDS mode is enabled along with column binning
(bin 2 or bin 4, R0x0D[3:2]), the packet size remains the
same but the serial pixel data stream repeats itself depending
on whether 2X or 4X binning is set:
For bin 2, LVDS outputs double the expected data
(pixel 0,0 is output twice in sequence, followed by pixel
0,1 twice, . . .).
For bin 4, LVDS outputs 4 times the expected data
(pixel 0,0 is output 4 times in sequence followed by
pixel 0,1 times 4, . . .).
The receiving hardware will need to undersample the
output stream getting data either every 2 clocks (bin 2) or
every 4 (bin 4) clocks.
If the sensor provides a pixel whose value is 0,1, 2, or 3
(that is, the same as a reserved word) then the outgoing serial
pixel value is switched to 4


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