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AD7171 Scheda tecnica(PDF) 8 Page - Analog Devices |
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AD7171 Scheda tecnica(HTML) 8 Page - Analog Devices |
8 / 17 page Data Sheet AD7171 Rev. C | Page 7 of 16 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. CONNECT EXPOSED PAD TO GROUND. SCLK AIN(+) AIN(–) REFIN(+) GND VDD GND REFIN(–) PDRST DOUT/RDY 1 2 3 4 5 10 9 8 7 6 AD7171 TOP VIEW (Not to Scale) Figure 5. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 SCLK Serial Clock Input. This serial clock input is for data transfers from the ADC. The SCLK has a Schmitt-triggered input. The serial clock can be continuous with all data transmitted in a constant train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted from the ADC in smaller batches of data. 2 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. In addition, it functions as a serial data output pin to access the data register of the ADC. Eight status bits accompany each data read. See Figure 13 for further details. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that new data is available. If the data is not read after the conversion, the pin goes high before the next update occurs. 3 AIN(+) Analog Input. AIN(+) is the positive terminal of the differential analog input pair AIN(+)/AIN(−). 4 AIN(−) Analog Input. AIN(−) is the negative terminal of the differential analog input pair AIN(+)/AIN(−). 5 REFIN(+) Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(–). The nominal reference voltage (REFIN(+) − REFIN(−)) is 5 V, but the device can function with a reference of 0.5 V to VDD. 6 REFIN(−) Negative Reference Input. 7, 10 GND Ground Reference Point. 8 VDD Supply Voltage, 2.7 V to 5.25 V. 9 PDRST Power-Down/Reset. When this pin is low, the ADC is placed in power-down mode. All the logic on the chip is reset and the DOUT/RDY pin is tristated. When PDRST is high, the ADC is taken out of power-down mode. The on-chip clock powers up and settles, and the ADC continuously converts. The internal clock requires 1 ms approximately to power up. EPAD Exposed Pad. Connect exposed pad to ground. |
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