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AD2S44-TM18B Scheda tecnica(PDF) 9 Page - Analog Devices |
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AD2S44-TM18B Scheda tecnica(HTML) 9 Page - Analog Devices |
9 / 13 page AD2S44 Data Sheet Rev. B | Page 8 of 12 OUTPUT ENABLE (OE) OE is the output enable input; the signal is active low. When set to Logic 1, DB1 to DB14 are in high impedance state. When OE is set to Logic 0, DB1 to DB14 represent the angle of the transducer shaft to within the stated accuracy of the converter (see bit weights in Table 4). Data becomes valid 640 ns after the OE is switched. Timing information is shown in Figure 4 and Figure 5 and detailed in Table 1. Table 4. Bit Weight Bit No. Weight (Degrees) 1 (MSB) 180.0000 2 90.0000 3 45.0000 4 22.5000 5 11.2500 6 5.6250 7 2.8125 8 1.4063 9 0.7031 10 0.3516 11 0.1758 12 0.0879 13 0.0439 14 ( LSB) 0.0220 CHANNEL B VALID* CHANNEL A VALID* tR tS tS OE A/B DATA BITS (1 TO 14) *CONVERTER DATA OUTPUT IS INHIBITED FROM UPDATES DURING CHANNEL VALID. Figure 4. Repetitive Reading of One Channel OE A/B DATA BITS (1 TO 14) DATA VALID* DATA VALID* tR tS tP *CONVERTER DATA OUTPUT IS INHIBITED FROM UPDATES DURING CHANNEL VALID. Figure 5. Alternative Reading of Each Channel BUILT-IN TEST (BIT) The BIT is the built-in test error output, which provides an over- velocity or fault indication signal for the channel selected via A/B. The error voltage of each channel is continuously monitored. When the error exceeds ±50 bits for the currently selected channel, the BIT output goes low, indicating that an error greater than approx- imately one angular degree exists, and the data is, therefore, invalid. The BIT signal has a built-in hysteresis; that is, the error required to set the BIT is greater than the error required for it to be cleared. The BIT is set when the error exceeds 55 LSBs and is cleared when the error goes below 45 LSBs. This mode of operation guarantees that the BIT does not flicker when the error threshold is crossed. The BIT is valid for the selected channel approximately 50 ns after the change in the state of A/B. In most instances, the error condi- tion that sets the BIT must persist for at least one period of the reference signal prior to the BIT responding to the condition. Table 5. BIT Output Faults Condition Description Power-Up Transient Response The BIT returns to a logic high state after the AD2S44 position output synchronizes with the angle input to within 1°. Normally, the BIT is low at power-up for a period less than or equal to the large signal step response settling time of the AD2S44 after the ±VS supplies have stabilized to within 5% of their final values. Step Input > 1° The BIT returns to a logic high state after the selected channel of the AD2S44 has settled to within 1° of the input angle resulting from an instantaneous step. Excessive Velocity The BIT is driven to a logic low if the maximum tracking rate of the AD2S44 is exceeded (20 rps typical). Signal Failure The BIT may be driven to a logic low state if all signal voltages to the selected channel are lost. Converter/System Failure Any failure that causes the AD2S44 to fail to track the input synchro/resolver angles drives the BIT to a logic low. This may include, but is not limited to, acceleration conditions, poor supply voltage regulation, or excessive noise on the signal connections. |
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