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AD6676 Scheda tecnica(PDF) 7 Page - Analog Devices |
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AD6676 Scheda tecnica(HTML) 7 Page - Analog Devices |
7 / 90 page Data Sheet AD6676 Rev. D | Page 7 of 90 DIGITAL HIGH SPEED SERDES SPECIFICATIONS VDD1 = VDDL = VDDC = VDDQ = 1.1 V, VDDD = VDDHSI = 1.1 V, VDD2 = 2.5 V, VDDIO = 1.8 V, unless otherwise noted. Table 2. Parameter Symbol Temp. Min Typ Max Unit HIGH SPEED SERIAL INPUT/OUTPUT Line Rate 1.6668 5.333 Gbps Dual Lane Data Output Period or Unit Interval UI Full 1/(20 × fDATA_IQ)1 sec Single Lane Data Output Period or Unit Interval UI Full 1/(40 × fDATA_IQ)1 sec Data Output Duty Cycle 25°C 50 % Data Valid Time 25°C 0.78 UI PLL Lock Time 25°C 4 μs Wake-Up Time (Standby) 25°C 5 μs Wake-Up Time (Power-Down) 25°C 2.5 ms Pipeline Delay (Latency) Full 32.3 1/fDATA_IQ1 Deterministic Jitter 25°C 9 ps Random Jitter at 5.333 Gbps 25°C 0.7 ps rms Output Rise/Fall Time 25°C 45 ps SYNCINB± Falling Edge to First K.28 Characters 25°C 4 Multiframes CGS Phase K.28 Characters Duration 25°C 1 Multiframes DIGITAL OUTPUTS (SERDOUT0±, SERDOUT1±) Logic Compliance Full CML Differential Output Voltage VOD Full 360 750 mV p-p Output Offset Voltage, ANSI Mode VOS Full 0.75 VDDHSI/2 1.05 V Differential Termination Impedance 25°C 100 Ω SYSREF INPUT (SYSREF±) Logic Compliance LVDS/PECL Differential Input Voltage Full 0.6 1.2 1.8 V p-p Differential Input Impedance2 25°C 35/2 kΩ||pF Input Common-Mode Voltage 0.8 0.85 2.0 V SYNCIN INPUT (SYNCINB+, SYNCINB−) Logic Compliance3 CMOS/LVDS CMOS Input Voltage High VIH 0.65 × VDDIO V CMOS Input Voltage Low VIL 0.35 × VDDIO V LVDS Differential Input Voltage Full 0.6 1.2 1.8 V p-p LVDS Differential Input Impedance 25°C 100||1 Ω||pF LVDS Input Common-Mode Voltage 0.8 0.85 2.0 V LVDS Input Common-Mode Impedance 25°C 1||1 kΩ||pF SYSREF (SYSREF±) TIMING REQUIREMENTS4 Clock Synthesizer Disabled Setup Time tSU_SR 25°C 0.16 ns Hold Time tH_SR 25°C 0.84 ns Clock Synthesizer Enabled Setup Time tSU_SR 25°C 0.5 ns Hold Time tH_SR 25°C 0.5 ns 1 FDATA_IQ corresponds to the complex output data rate (that is, FADC/DEC_FACTOR). Latency specification also includes ADC and digital filters delays. See Table 15 2 The SYSREF± input requires an external differential resistor for proper termination. 3 Set via Register 0x1E7, Bit 2, with CMOS being the default setting. 4 SYSREF± setup and hold times are defined with respect to the rising SYSREF± edge and rising clock edge. Positive setup time leads the clock edge. Positive hold time also lags the clock rising edge. Note that the hold time takes into consideration that the internal clock signal used to sample SYSREF operates at FADC/2; thus, SYSREF± must remain high for at least two FADC clock cycles. |
Codice articolo simile - AD6676_17 |
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Descrizione simile - AD6676_17 |
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