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CS62180B-IL Scheda tecnica(PDF) 7 Page - Cirrus Logic |
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CS62180B-IL Scheda tecnica(HTML) 7 Page - Cirrus Logic |
7 / 50 page GENERAL DESCRIPTION The CS62180B is a monolithic CMOS circuit that encodes and decodes T1 (1.544 MHz) digi- tal transmission formats for SF(D4 ®) (193S: 12 frames per superframe), ESF (193E: 24 frames per superframe), SLC-96® DDS® T1DM (T1DM: 12 frames per superframe plus unique channel number 24) framing formats. The CS62180B provides full support for individual clear channels, bit- robbed signaling, alarm detection and generation, zero suppression, and idle channels. An overview of the 193S, 193E, SLC-96 ® and T1DM framing formats is provided in the Applications Section. The device provides independent transmit and receive sides, with a shared serial controller in- terface for use with a host processor. A hardware mode is also available for operation independent of a host controller. The SLC-96 ® and T1DM formats can be selected only via the CS62180B serial controller interface. The serial interface provides access to 16 on- chip control and status registers. The control registers are used to configure global parameters such as the framing format and zero suppression mode, as well as transmitter or receiver specific parameters. A hardware interrupt is provided, which can be configured via interrupt mask and status registers to signal any combination of alarm conditions. Transmitter commands include enabling external framing bit, CRC, or S-bit insertion, declaring individual DS0 channels clear and/or idle, and enabling yellow and blue alarm modes in differ- ent formats. The receiver can be configured to replace individual incoming channels with idle or digital milliwatt ( µ-LAW) codes, and a large variety of resync options are provided. Bipolar violations, CRC and framing errors are automat- ically counted in another set of registers which can be arbitrarily reset via the serial interface to provide variable saturation points. The Receive Status Register (RSR) provides data on all error and alarm conditions, and in conjunction with the Receive Interrupt Mask Register (RIMR), can be configured to signal an interrupt on INT (SLC96: 72 frames per superframe) and in response to any alarm condition. Note: there are two different naming conventions in practice concerning the numbering of bits within a word. The most common convention in EE and Computer Science is to number the bits as 0 - 7, starting from the LSB. This is the con- vention used throughout this data sheet when referring to register bits. A different convention is used in the telecom literature when referring to the bits in a digital transmission stream. In this case, they are numbered 1 - 8, starting from the MSB. This convention is maintained in this data sheet whenever referring to the bits of a DS0 channel word. CS62180B ENHANCEMENTS Enhancements made in the CS62180B include the following. The SLC-96 ® and DDS® T1DM framing formats are supported in host mode. The AIS (Blue Code) detection is made compatible with TR-TSY-000191 requirements (unframed all ones), and a received-blue-alarm output pin is added to the PLCC package. The Receive Carrier Loss detection criteria is made compatible with the industry standard requirement of 175 ±75 ze- ros. The receiver line code decoder is now universal. The decoder will automatically decode either AMI or B8ZS. The CS62180B B8ZS con- trol option controls only the transmitter’s encoder. The universal decoder simplifies the provisioning of B8ZS in the network. Lastly, the serial control interface was simplified. When writing data bytes on SDI, it is no longer neces- sary to have SDI valid for both the rising and falling edges of SCLK. Rather, SDI need be sta- ble only on the rising edge of SCLK. CS62180B DS225PP2 7 |
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