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SN74AUP1G240DBVT Scheda tecnica(PDF) 1 Page - Texas Instruments |
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SN74AUP1G240DBVT Scheda tecnica(HTML) 1 Page - Texas Instruments |
1 / 44 page A Y OE 1 2 4 Product Folder Order Now Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. SN74AUP1G240 SCES627D – MARCH 2005 – REVISED OCTOBER 2017 SN74AUP1G240 Low-Power Single Inverter With 3-State Output 1 1 Features 1 • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) • Available in the Texas Instruments NanoStar™ Package • Low Static-Power Consumption – ICC = 0.9 µA Maximum • Low Dynamic-Power Consumption – Cpd = 4.2 pF at 3.3 V Typical • Low Input Capacitance – CI = 1.5 pF Typical • Low Noise – Overshoot and Undershoot <10% of VCC • Input-Disable Feature Allows Floating Input Conditions • Ioff Supports Partial Power-Down-Mode Operation • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input • Wide Operating VCC Range of 0.8 V to 3.6 V • Optimized for 3.3-V Operation • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation • tpd = 4.7 ns Maximum at 3.3 V • Suitable for Point-to-Point Applications 2 Applications • Grid infrastructure • Telecom Infrastructure • Medical, Healthcare, and Fitness • Factory Automation and Control • Printers and Other Peripherals 3 Description The AUP family is TI's premier solution to the industry's low power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see AUP – The Lowest- Power Family ). This buffer/driver is a single line driver with a 3-state output. The output is disabled when the output- enable (OE) input is high. This device has the input- disable feature, which allows floating input signals. To assure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN74AUP1G240DBV SOT-23 (5) 1.60 mm × 2.90 mm SN74AUP1G240DCK SC70 (5) 1.25 mm × 2.00 mm SN74AUP1G240DRY SON (6) 1.00 mm × 1.45 mm SN74AUP1G240DSF SON (6) 1.00 mm × 1.00 mm SN74AUP1G240YFP DSBGA (6) 0.76 mm × 1.16 mm SN74AUP1G240YZP DSBGA (5) 0.89 mm × 1.39 mm SN74AUP1G240DPW(2) X2SON (5) 0.80 mm × 0.80 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Package preview only Logic Diagram (Positive Logic) |
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