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SN74AUP1G126DSFR Scheda tecnica(PDF) 1 Page - Texas Instruments |
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SN74AUP1G126DSFR Scheda tecnica(HTML) 1 Page - Texas Instruments |
1 / 43 page 1 2 OE A 4 Y Product Folder Order Now Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74AUP1G126 SCES596G – JULY 2004 – REVISED AUGUST 2017 SN74AUP1G126 Low-Power Single Bus Buffer Gate With Tri-State Output 1 1 Features 1 • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Performance Tested Per JESD 22 − – 2000-V Human-Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) • Available in the Texas Instruments NanoStar™ Package • Low Static-Power Consumption (ICC = 0.9 µA Maximum) • Low Dynamic-Power Consumption (Cpd = 4 pF Typical at 3.3 V) • Low Input Capacitance (Ci = 1.5 pF Typical) • Low Noise – Overshoot and Undershoot <10% of VCC • Input-Disable Feature Allows Floating Input Conditions • Ioff Supports Partial-Power-Down Mode Operation • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input • Wide Operating VCC Range of 0.8 V to 3.6 V • Optimized for 3.3-V Operation • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation • tpd = 4.6 ns Maximum at 3.3 V • Suitable for Point-to-Point Applications 2 Applications • Audio Dock: Portable • BluRay™ Players and Home Theaters • Personal Digital Assistant (PDA) • Power: Telecom/Server AC/DC Supply: Single Controller: Analog and Digital • Solid-State Drive (SSD): Client and Enterprise • TV: LCD/Digital and High-Definition (HDTV) • Tablet: Enterprise • Wireless Headsets, Keyboards, and Mice 3 Description The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see AUP – The Lowest- Power Family and Excellent Signal Integrity ). This bus buffer gate is a single line driver with a 3- state output. The output is disabled when the output- enable (OE) input is low. This device has the input- disable feature, which allows floating input signals. To assure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN74AUP1G126DRL SOT-5X3 (5) 1.60 mm × 1.20 mm SN74AUP1G126DBV SOT-23 (5) 1.60 mm × 2.90 mm SN74AUP1G126DCK SC70 (5) 1.25 mm × 2.00 mm SN74AUP1G126DRY SON (6) 1.00 mm × 1.45 mm SN74AUP1G126DSF SON (6) 1.00 mm × 1.00 mm SN74AUP1G126YFP DSBGA (6) 0.76 mm × 1.16 mm SN74AUP1G126YZP DSBGA (5) 0.89 mm × 1.39 mm SN74AUP1G126DPW X2SON (5) 0.80 mm × 0.80 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive Logic) |
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