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FAN4174IP5X_NL Scheda tecnica(PDF) 9 Page - Fairchild Semiconductor |
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FAN4174IP5X_NL Scheda tecnica(HTML) 9 Page - Fairchild Semiconductor |
9 / 14 page FAN4174/FAN4274 Rev. 2D 9 www.fairchildsemi.com Application Information General Description The FAN4174 amplifier family are single supply, general pur- pose, voltage-feedback amplifiers. Fabricated on a bi-CMOS process. The family features a rail-to-rail input and output and is unity gain stable. The typical non-inverting circuit schematic is shown in Figure 1. Figure 1. Typical Non-inverting Configuration Input Common Mode Voltage The common mode input range extends to 300mV below ground and to 100mV above Vs, in single supply operation. Exceeding these values will not cause phase reversal. However, if the input voltage exceeds the rails by more than 0.5V, the input ESD devices will begin to conduct. The output will stay at the rail during this overdrive condition. If the absolute maximum input voltage (700mV beyond either rail) is exceeded, externally limit the input current to ±5mA as shown in Figure 2. Figure 2. Circuit for Input Current Protection Power Dissipation The maximum internal power dissipation allowed is directly related to the maximum junction temperature. If the maximum junction temperature exceeds 150°C, some performance degradation will occur. If the maximum junction temperature exceeds 150°C for an extended time, device failure may occur. Overdrive Recovery Overdrive of an amplifier occurs when the output and/or input ranges are exceeded. The recovery time varies based on whether the input or output is overdriven and by how much the ranges are exceeded. The FAN4174 will typically recover in less than 500ns from an overdrive condition. Figure 3 shows the FAN4174 amplifier in an overdriven condition. Figure 3. Overdrive Recovery Driving Capacitive Loads The Frequency Response vs. CL plot, illustrates the response of the FAN4174 amplifier family. A small series resistance (Rs) at the output of the amplifier, illustrated in Figure 4, will improve stabil- ity and settling performance. Rs values in the Frequency Response vs. CL plot were chosen to achieve maximum band- width with less than 2dB of peaking. For maximum flatness, use a larger Rs. Capacitive loads larger than 500pF require the use of Rs. Figure 4. Typical Topology for driving a capacitive load Driving a capacitive load introduces phase-lag into the output signal, which reduces phase margin in the amplifier. The unity gain follower is the most sensitive configuration. In a unity gain follower configuration, the FAN4174 amplifier family requires a 300 Ω series resistor to drive a 100pF load. + - FAN4174 Rf 0.01 µF 6.8 µF Out In +Vs + Rg Rout - + 10k Ω Vo Vin Time (1 µs/div) Output Input G = 5 VS = 2.7V 0.1 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 + - Rf Rg Rs CL RL |
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