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AD10200 Scheda tecnica(PDF) 11 Page - Analog Devices |
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AD10200 Scheda tecnica(HTML) 11 Page - Analog Devices |
11 / 20 page REV. B AD10200 –10– APPLICATION NOTES Theory of Operation The AD10200 is a high-dynamic range dual 12-bit, 105 MHz subrange pipeline converter that uses switched capacitor architecture. The analog input section uses AINA2/AINB2 at 2.048 V p-p with an input impedance of 50 Ω. The analog input includes an ac-coupled wide-band 1:1 transformer, which provides high-dynamic range and SNR while maintaining VSWR and gain flatness. The ADC includes a high-bandwidth linear track/ hold that gives excellent spurious performance up to and beyond the Nyquist rate. The high-bandwidth track/hold has a low jitter of 0.25 ps rms, leading to excellent SNR and SFDR performance. AC-coupled differential PECL/ECL encode inputs are recom- mended for optimum performance. USING THE AD10200 ENCODE Input Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A track/hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock will be combined with the desired signal at the A/D output. For that reason, considerable care has been taken in the design of the ENCODE input of the AD10200, and the user is advised to give commensurate thought to the clock source. The ENCODE input are fully TTL/CMOS compatible. For opti- mum performance, the AD10200 must be clocked differentially. Note that the ENCODE inputs cannot be driven directly from PECL level signals (VIHD is 3.5 V max). PECL level signals can easily be accommodated by ac coupling as shown in Figure 6. Good performance is obtained using an MC10EL16 in the circuit to drive the encode inputs. GND 510 510 0.1 F 0.1 F PECL GATE ENCODE ENCODE AD10200 Figure 6. AC Coupling to ENCODE Inputs ENCODE Voltage Level Definition The voltage level definitions for driving ENCODE and ENCODE in differential mode are shown in Figure 7. ENCODE Inputs Differential Signal Amplitude (VID) 500 mV min, 750 mV nom High Differential Input Voltage (VIHD) 5.0 V max Low Differential Input Voltage (VILD) 0 V min Common-Mode Input (VICN) 1.25 V min, 1.6 V nom ENCODE 0.1 F VIHS VILS ENCODE ENCODE VID VIHD VILD VICM Figure 7. Differential Input Levels Often, the cleanest clock source is a crystal oscillator producing a pure sine wave. In this configuration, or with any roughly symmetrical clock input, the input can be ac-coupled and biased to a reference voltage that also provides the ENCODE. This ensures that the reference voltage is centered on the encode signal. Digital Outputs The digital outputs are TTL/CMOS-compatible and a separate output power supply pin supports interfacing with 3.3 V logic. Analog Input The analog input is a single ended ac-coupled high performance 1:1 transformer with an input impedance of 50 Ω to 105 MHz. The nominal full scale input is 2.048 V p-p. Special care was taken in the design of the analog input section of the AD10200 to prevent damage and corruption of data when the input is overdriven. Voltage Reference A stable and accurate 2.5 V voltage reference is designed into the AD10200 (VREFOUT). An external voltage reference is not required. Timing The AD10200 provides latched data outputs, with 10 pipeline delays. Data outputs are available one propagation delay (tPD) after the rising edge of the encode command (see Figure 1). The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD10200; these transients can detract from the converter's dynamic performance. The minimum guaranteed conversion rate of the AD10200 is 10 MSPS. At internal clock rates below 10 MSPS, dynamic performance may degrade. Therefore, input clock rates below 10 MHz should be avoided. GROUNDING AND DECOUPLING Analog and Digital Grounding Proper grounding is essential in any high speed, high resolution system. Multilayer printed circuit boards (PCBs) are recom- mended to provide optimal grounding and power schemes. The use of ground and power planes offers distinct advantages: 1. The minimization of the loop area encompassed by a signal and its return path. 2. The minimization of the impedance associated with ground and power paths. 3. The inherent distributed capacitor formed by the power plane, PCB insulation and ground plane. These characteristics result in both a reduction of electromagnetic interference (EMI) and an overall improvement in performance. It is important to design a layout that prevents noise from cou- pling to the input signal. Digital signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. The PCB should have a ground plane covering all unused portions of the component side of the board to pro- vide a low impedance path and manage the power and ground currents. The ground plane should be removed from the area near the input pins to reduce stray capacitance. |
Codice articolo simile - AD10200_17 |
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Descrizione simile - AD10200_17 |
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