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AD9228ABCPZ-65 Scheda tecnica(PDF) 8 Page - Analog Devices

Il numero della parte AD9228ABCPZ-65
Spiegazioni elettronici  Serial LVDS 1.8 V A/D Converter
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD9228ABCPZ-65 Scheda tecnica(HTML) 8 Page - Analog Devices

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Data Sheet
AD9228
Rev. E | Page 7 of 56
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
AD9228-40
AD9228-65
Parameter1, 2
Temp
Min
Typ
Max
Min
Typ
Max
Unit
CLOCK3
Maximum Clock Rate
Full
40
65
MSPS
Minimum Clock Rate
Full
10
10
MSPS
Clock Pulse Width High (tEH)
Full
12.5
7.7
ns
Clock Pulse Width Low (tEL)
Full
12.5
7.7
ns
OUTPUT PARAMETERS3
Propagation Delay (tPD)
Full
2.0
2.7
3.5
2.0
2.7
3.5
ns
Rise Time (tR) (20% to 80%)
Full
300
300
ps
Fall Time (tF) (20% to 80%)
Full
300
300
ps
FCO Propagation Delay (tFCO)
Full
2.0
2.7
3.5
2.0
2.7
3.5
ns
DCO Propagation Delay (tCPD)4
Full
tFCO +
(tSAMPLE/24)
tFCO +
(tSAMPLE/24)
ns
DCO to Data Delay (tDATA)4
Full
(tSAMPLE/24) − 300
(tSAMPLE/24)
(tSAMPLE/24) + 300
(tSAMPLE/24) − 300
(tSAMPLE/24)
(tSAMPLE/24) + 300
ps
DCO to FCO Delay (tFRAME)4
Full
(tSAMPLE/24) − 300
(tSAMPLE/24)
(tSAMPLE/24) + 300
(tSAMPLE/24) − 300
(tSAMPLE/24)
(tSAMPLE/24) + 300
ps
Data to Data Skew
(tDATA-MAX − tDATA-MIN)
Full
±50
±150
±50
±150
ps
Wake-Up Time (Standby)
25°C
600
600
ns
Wake-Up Time (Power-Down)
25°C
375
375
μs
Pipeline Latency
Full
8
8
CLK
cycles
APERTURE
Aperture Delay (tA)
25°C
500
500
ps
Aperture Uncertainty (Jitter)
25°C
<1
<1
ps rms
Out-of-Range Recovery Time
25°C
1
2
CLK
cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Measured on standard FR-4 material.
3 Can be adjusted via the SPI.
4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.


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