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74HC4024N Scheda tecnica(PDF) 10 Page - NXP Semiconductors |
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74HC4024N Scheda tecnica(HTML) 10 Page - NXP Semiconductors |
10 / 18 page 9397 750 13813 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 03 — 12 November 2004 10 of 18 Philips Semiconductors 74HC4024 7-stage binary ripple counter [1] CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. Tamb = −40 °C to +125 °C tPHL, tPLH propagation delay CP to Q0 see Figure 6 VCC = 2.0 V - - 265 ns VCC = 4.5 V - - 53 ns VCC = 6.0 V - - 45 ns propagation delay Qn to Qn+1 see Figure 6 VCC = 2.0 V - - 120 ns VCC = 4.5 V - - 24 ns VCC = 6.0 V - - 20 ns tPHL propagation delay MR to Q0 see Figure 6 VCC = 2.0 V - - 300 ns VCC = 4.5 V - - 60 ns VCC = 6.0 V - - 51 ns tTHL, tTLH output transition time see Figure 6 VCC = 2.0 V - - 110 ns VCC = 4.5 V - - 22 ns VCC = 6.0 V - - 19 ns tW CP clock pulse width HIGH or LOW see Figure 6 VCC = 2.0 V 120 - - ns VCC = 4.5 V 24 - - ns VCC = 6.0 V 20 - - ns MR master reset pulse width HIGH see Figure 6 VCC = 2.0 V 120 - - ns VCC = 4.5 V 24 - - ns VCC = 6.0 V 20 - - ns trem removal time MR to CP see Figure 6 VCC = 2.0 V 75 - - ns VCC = 4.5 V 15 - - ns VCC = 6.0 V 13 - - ns fmax maximum clock frequency see Figure 6 VCC = 2.0 V 4.0 - - MHz VCC = 4.5 V 20 - - MHz VCC = 6.0 V 24 - - MHz Table 8: Dynamic characteristics …continued GND = 0 V; tr =tf = 6 ns; CL = 50 pF; see Figure 7. Symbol Parameter Conditions Min Typ Max Unit |
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