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AD9253BCPZ-125 Scheda tecnica(PDF) 3 Page - Analog Devices |
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AD9253BCPZ-125 Scheda tecnica(HTML) 3 Page - Analog Devices |
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3 / 41 page  AD9253 Data Sheet Rev. B | Page 2 of 40 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Timing Specifications .................................................................. 6 Absolute Maximum Ratings.......................................................... 10 Thermal Resistance .................................................................... 10 ESD Caution................................................................................ 10 Pin Configuration and Function Descriptions........................... 11 Typical Performance Characteristics ........................................... 13 AD9253-80 .................................................................................. 13 AD9253-105 ................................................................................ 15 AD9253-125 ................................................................................ 17 Equivalent Circuits......................................................................... 20 Theory of Operation ...................................................................... 21 Analog Input Considerations.................................................... 21 Voltage Reference ....................................................................... 22 Clock Input Considerations...................................................... 23 Power Dissipation and Power-Down Mode ........................... 25 Digital Outputs and Timing ..................................................... 26 Output Test Modes..................................................................... 29 Serial Port Interface (SPI).............................................................. 30 Configuration Using the SPI..................................................... 30 Hardware Interface..................................................................... 31 Configuration Without the SPI ................................................ 31 SPI Accessible Features.............................................................. 31 Memory Map .................................................................................. 32 Reading the Memory Map Register Table............................... 32 Memory Map Register Table..................................................... 33 Memory Map Register Descriptions........................................ 36 Applications Information .............................................................. 38 Design Guidelines ...................................................................... 38 Power and Ground Recommendations................................... 38 Clock Stability Considerations ................................................. 38 Exposed Pad Thermal Heat Slug Recommendations............ 38 VCM............................................................................................. 38 Reference Decoupling................................................................ 38 SPI Port........................................................................................ 38 Crosstalk Performance .............................................................. 39 Outline Dimensions....................................................................... 40 Ordering Guide .......................................................................... 40 REVISION HISTORY 10/15—Rev. A to Rev. B Added Note 4, Table 4...................................................................... 6 Changes to Digital Outputs and Timing Section ....................... 27 Changes to Clock Stability Considerations Section................... 38 9/14—Rev. 0 to Rev. A Changes to Table 2............................................................................ 4 Added Propagation Delay Parameters of 1.5 ns (Min) and 3.1 ns (Max); Table 4, Changed tSSYNC from 0.24 ns Typ to 1.2 ns Min, and Changed tHSYNC from 0.40 ns Typ to −0.2 ns Min; Table 5 ......................................................................... 6 Changes to Figure 3................................................................................7 Changes to Figure 5........................................................................... 8 Changes to Pin 9 to Pin 14 and Pin 23 to Pin 28 Descriptions ......11 Changes to Figure 48 and Figure 49 ............................................ 20 Changes to Clock Input Options Section.................................... 23 Changes to Jitter Considerations Section.................................... 25 Changes to Digital Outputs and Timing Section....................... 26 Changes to Table 11 ....................................................................... 28 Changes to Table 12 ....................................................................... 29 Changes to Channel-Specific Registers Section......................... 32 Changes to Output Phase (Register 0x16) Section .................... 36 Changes to Resolution/Sample Rate Override (Register 0x100) Section.............................................................................................. 37 Added Clock Stability Considerations Section........................... 38 Updated Outline Dimensions....................................................... 40 10/11—Revision 0: Initial Version |
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