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TC55V400AFT-55 Scheda tecnica(PDF) 8 Page - Toshiba Semiconductor |
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TC55V400AFT-55 Scheda tecnica(HTML) 8 Page - Toshiba Semiconductor |
8 / 11 page TC55V400AFT-55,-70 2001-09-04 8/11 WRITE CYCLE 4 ( , CONTROLLED) (See Note 4) Note: (1) R/W remains HIGH for the read cycle. (2) If CE1 goes LOW(or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs will remain at high impedance. (3) If CE1 goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the outputs will remain at high impedance. (4) If OE is HIGH during the write cycle, the outputs will remain at high impedance. (5) Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. UB LB Address R/W tWC tAS tWR tWP 1 CE DOUT VALID DATA IN DIN tDS tDH Hi-Z Hi-Z tCW CE2 tBW tBE tCOE tODW UB , LB tCW (See Note 5) |
Codice articolo simile - TC55V400AFT-55 |
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