AD7091R-5_17 datasheet(9/35 Pages) AD

Il numero della parte	AD7091R-5

Spiegazioni elettronici	4-Channel, I 2 C, Ultralow Power 12-Bit ADC in 20-Lead LFCSP/TSSOP

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AD7091R-5

Data Sheet

Rev. 0 | Page 8 of 34

Pin No.

Mnemonic

Description

TSSOP

LFCSP

16

14

AS1

I2C Address Bit 1. Together with AS0, the logic state of these two inputs selects a unique I2C

address for the AD7091R-5. The device address depends on the logic state of these pins.

17

15

SDA

Serial Data Input/Output. This open-drain output requires a pull-up resistor. The output coding is

straight binary for the voltage channels.

18

16

SCL

Digital Input Serial I2C Bus Clock. This input requires a pull-up resistor. The data transfer rate in I2C

mode is compatible with both 100 kHz (standard mode) and 400 kHz (fast mode) operating

modes.

19

17

CONVST/GPO1

This is a multifunction pin determined by the configuration register and mode of conversion.

Convert Start Input Signal (CONVST). Edge triggered logic input. The falling edge of CONVST

places the ADC into hold mode and initiates a conversion. The logic level of CONVST at EOC

controls the power modes of the AD7091R-5.

General-Purpose Digital Output 1 (GPO1). When in command or autocycle mode, this pin can

function as a general-purpose digital output.

20

18

VDRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the

interface operates. Connect decoupling capacitors between VDRIVE and GND. The typical

recommended values are 10 µF and 0.1 µF. The voltage range on this pin is 1.8 V to 5.25 V and

may differ from the voltage range at VDD, but must never exceed it by more than 0.3 V.

N/A1

21

EPAD

Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be

soldered to GND.

1

N/A means not applicable.

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