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AD7761BSTZ-RL7 Scheda tecnica(PDF) 8 Page - Analog Devices |
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AD7761BSTZ-RL7 Scheda tecnica(HTML) 8 Page - Analog Devices |
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8 / 76 page  Data Sheet AD7761 Rev. A | Page 7 of 75 Parameter Test Conditions/Comments Min Typ Max Unit LVDS Clock2 RL = 100 Ω Differential Input Voltage 100 650 mV Common-Mode Input Voltage 800 1575 mV Absolute Input Voltage 1.88 V ADC RESET2 ADC Start-Up Time After Reset6 Time to first DRDY, fast mode, decimation by 32 1.58 1.66 ms Minimum RESET Low Pulse Width tMCLK = 1/MCLK 2 × tMCLK LOGIC INPUTS Input Voltage2 High, VINH 0.65 × IOVDD V Low, VINL 2.25 V < IOVDD < 3.6 V 0.7 V 1.72 V < IOVDD < 1.88 V 0.4 V Hysteresis2 2.25 V < IOVDD < 3.6 V 0.04 0.09 V 1.72 V < IOVDD < 1.88 V 0.04 0.2 V Leakage Current −10 +0.03 +10 µA RESET pin7 −10 +10 µA LOGIC OUTPUTS Output Voltage2 High, VOH ISOURCE = 200 μA 0.8 × IOVDD V Low, VOL ISINK = 400 µA 0.4 V Leakage Current Floating state −10 +10 µA Output Capacitance Floating state 10 pF SYSTEM CALIBRATION2 Full-Scale Calibration Limit 1.05 × VREF V Zero-Scale Calibration Limit −1.05 × VREF V Input Span 0.4 × VREF 2.1 × VREF V POWER REQUIREMENTS Power Supply Voltage AVDD1 − AVSS 4.5 5.0 5.5 V AVDD2 − AVSS 2.0 2.25 to 5.0 5.5 V AVSS − DGND −2.75 0 V IOVDD − DGND 1.72 2.5 to 3.3 or 1.8 3.6 V POWER SUPPLY CURRENTS Maximum output data rate, CMOS MCLK, eight DOUTx signals, all supplies at maximum voltages, all channels in Channel Mode A Eight Channels Active Fast Mode AVDD1 Current Precharge reference buffers off 36 40 mA Precharge reference buffers on 57.5 64 mA AVDD2 Current 37.5 40 mA IOVDD Current Wideband filter 63 69 mA Sinc5 filter2 27 29 mA Median Mode AVDD1 Current Precharge reference buffers off 18.5 mA Precharge reference buffers on 29 mA AVDD2 Current 21.3 mA IOVDD Current Wideband filter 34 mA Sinc5 filter 16 mA |
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