ESS Technology, Inc.

SAM0378-053001

7

ES4228/ES4227 PRODUCT BRIEF

RSD

33

O

Dual-purpose pin. RSD is the receive audio data input.

SEL_PLL0

I

SEL_PLL0 along with SEL_PLL1 select the PLL clock frequency for the DCLK output.

See the table for pin number 23.

RBCK

37

O

Dual-purpose pin. RBCK is the receive audio bit clock.

SER_IN

I

SER_IN is the serial input DSC mode.

0 - Parallel DSC mode.

1 - Serial DSC mode.

VSSAA

41,51

I

Audio Analog Ground.

VCM

42

I

ADC Common Mode Reference (CMR) buffer output. CMR is approximately 2.25 V.

Bypass to analog ground with 47

µF electrolytic in parallel with 0.1 µF.

VREFP

43

I

DAC and ADC maximum reference. Bypass to VCMR with 10

µF in parallel with 0.1 µF.

VCCAA

44

I

Analog VCC, 5 V.

AOR+,

AOR-

45, 46

O

Right channel output.

AOL-, AOL+

47, 48

O

Left channel output.

MIC2

49

I

Microphone input 2.

MIC1

50

I

Microphone input 1.

VREF

52

I

Internal resistor divider generates Common Mode Reference (CMR) voltage. Bypass to

analog ground with 0.1

µF.

VREFM

53

I

DAC and ADC minimum reference. Bypass to VCMR with 10

µF in parallel with 0.1 µF.

RSET

54

I

Full scale DAC current adjustment.

COMP

55

I

Compensation pin.

VSSAV

56:57, 62:63

I

Video analog ground

CDAC

58

O

Modulated chrominance output.

VCCAV

59, 60

I

5.0V video power supply.

YDAC

61

O

Y luminance data bus for screen video port.

VDAC

64

O

Composite video output.

ACAP

65

I

Audio CAP

XOUT

71

O

27 MHz crystal output.

XIN

74

I

27 MHz crystal input.

PCLK

79

I/O

13.5 MHz pixel clock.

2XPCLK

80

I/O

Doubled 27 MHz pixel clock.

HSYNC#

82

O

Horizontal sync.

VSYNC#

84

O

Vertical sync.

YUV[7:0]

86:89, 92, 94, 96,

98

I

YUV data bus for screen video port.

Table 2

ES4227 Pin Descriptions List (Continued)

Name

Number

I/O

Definition