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CD40161BCJ Scheda tecnica(PDF) 3 Page - National Semiconductor (TI) |
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CD40161BCJ Scheda tecnica(HTML) 3 Page - National Semiconductor (TI) |
3 / 8 page DC Electrical Characteristics CD40160BCCD40161BCCD40162BCCD40163BC (Note 2) (Continued) Limits Symbol Parameter Conditions b 40 C a 25 C a 85 C Units Min Max Min Typ Max Min Max VIH High Level Input VDDe5V VOe05V or 45V 35 35 35 V Voltage VDDe10V VOe1V or 9V 70 70 70 V VDDe15V VOe15V or 135V 110 110 110 V IOL Low Level Output VDDe5V VOe04V 052 044 088 036 mA Current (Note 3) VDDe10V VOe05V 13 11 225 09 mA VDDe15V VOe15V 36 30 88 24 mA IOH High Level Output VDDe5V VOe46V b 052 b 044 b 088 b 036 mA Current (Note 3) VDDe10V VOe95V b 13 b 11 b 225 b 09 mA VDDe15V VOe135V b 36 b 30 b 88 b 24 mA IIN Input Current VDDe15V VINe0V b 030 b 10b5 b 030 b 10 m A VDDe15V VINe15V 030 10b5 030 10 m A AC Electrical Characteristics TA e 25 C CL e 50 pF RL e 200k unless otherwise specified Symbol Parameter Conditions Min Typ Max Units tPHL or tPLH Propagation Delay Time from VDD e 5V 250 400 ns Clock to Q VDD e 10V 100 160 ns VDD e 15V 80 130 ns tPHL or tPLH Propagation Delay Time from VDD e 5V 290 450 ns Clock to Carry Out VDD e 10V 120 190 ns VDD e 15V 100 160 ns tPHL or tPLH Propagation Delay Time from T VDD e 5V 180 290 ns Enable to Carry Out VDD e 10V 70 130 ns VDD e 15V 60 110 ns tPHL Propagation Time from Clear to Q VDD e 5V 190 300 ns (CD40160B CD40161B Only) VDD e 10V 80 150 ns VDD e 15V 70 120 ns tSU Minimum Time Prior to Clock that VDD e 5V 120 ns Data or Load must be Present VDD e 10V 30 ns VDD e 15V 25 ns tSU Minimum Time Prior to Clock that VDD e 5V 170 280 ns Enable P or T must be Present VDD e 10V 70 120 ns VDD e 15V 60 100 ns tSU Minimum Time Prior to Clock that VDD e 5V 120 190 ns Clear must be Present (CD40162B VDD e 10V 50 80 ns CD40163B Only) VDD e 15V 40 70 ns tWL or tWH Maximum Clock Pulse Width VDD e 5V 125 250 ns VDD e 10V 45 90 ns VDD e 15V 35 70 ns tRCL or tFCL Maximum Clock Rise or Fall Time VDD e 5V 15 m s VDD e 10V 50 m s VDD e 15V 50 m s fCL Maximum Clock Frequency VDD e 5V 2 4 MHz VDD e 10V 55 11 MHz VDD e 15V 7 14 MHz tTHL or tTLH Transition Time All Outputs VDD e 5V 100 200 ns VDD e 10V 50 100 ns VDD e 15V 40 80 ns CIN Average Input Capacitance Any Input 50 75 pF CPD Power Dissipation Capacity (Note 4) 95 pF AC Parameters are guaranteed by DC correlated testing Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices should be operated at these limits The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 IOH and IOL are tested one output at a time Note 4 CPD determines the no load AC power consumption of any CMOS device For complete explanation see 54C74C Family Characteristics application note AN-90 3 |
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