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CS8182YDPSR5 Scheda tecnica(PDF) 5 Page - ON Semiconductor |
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CS8182YDPSR5 Scheda tecnica(HTML) 5 Page - ON Semiconductor |
5 / 12 page CS8182 http://onsemi.com 5 CIRCUIT DESCRIPTION ENABLE Function By pulling the VREF/ENABLE lead below 2.0 V typically, (see Figure 10 or Figure 11), the IC is disabled and enters a sleep state where the device draws less than 55 mA from supply. When the VREF/ENABLE lead is greater than 2.75 V, VOUT tracks the VREF/ENABLE lead normally. Output Voltage The output is capable of supplying 200 mA to the load while configured as a similar (Figure 7), lower (Figure 9), or higher (Figure 8) voltage as the reference lead. The Adj lead acts as the inverting terminal of the op amp and the VREF lead as the non−inverting. The device can also be configured as a high−side driver as displayed in Figure 12. Figure 7. Tracking Regulator at the Same Voltage VIN VOUT GND GND VREF/ GND GND Adj ENABLE Loads 5.0 V B+ C1* 1.0 mF C2** 10 mF VOUT, 200 mA VOUT + VREF Figure 8. Tracking Regulator at Higher Voltages VIN VOUT GND GND VREF/ GND GND Adj ENABLE Loads VREF B+ C1* 1.0 mF C2** 10 mF VOUT, 200 mA RA RF VOUT + VREF(1 ) RE RA ) C3*** 10 nF C3*** 10 nF Figure 9. Tracking Regulator at Lower Voltages VIN VOUT GND GND VREF/ GND GND Adj ENABLE Loads VREF B+ C1* 1.0 mF C2** 10 mF VOUT, 200 mA VOUT + VREF( R2 R1 ) R2 ) R2 R1 Figure 10. Tracking Regulator with ENABLE Circuit VIN VOUT GND GND VREF/ GND GND Adj ENABLE from MCU VREF B+ C1* 1.0 mF C2** 10 mF VOUT, 200 mA R C3*** 10 nF C3*** 10 nF Figure 11. Alternative ENABLE Circuit VIN VOUT GND GND VREF/ GND GND Adj ENABLE 10 mF Figure 12. High−Side Driver VIN VOUT GND GND VREF/ GND GND Adj ENABLE MCU B+ 200 mA VOUT + B )* VSAT ** C2 is required for stability. * C1 is required if the regulator is far from the power source filter. 5.0 V I/O NCV8501 6.0 V−40 V VIN 100 nF VREF (5.0 V) mC To Load (e.g. sensor) C1* 1.0 mF C3*** 10 nF C3*** 10 nF *** C3 is recommended for EMC susceptibility. |
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