Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

GS8182Q36BD-167I Scheda tecnica(PDF) 10 Page - GSI Technology

Il numero della parte GS8182Q36BD-167I
Spiegazioni elettronici  18Mb SigmaQuad-IITM Burst of 2 SRAM
Download  36 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  GSI [GSI Technology]
Homepage  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS8182Q36BD-167I Scheda tecnica(HTML) 10 Page - GSI Technology

Back Button GS8182Q36BD-167I Datasheet HTML 6Page - GSI Technology GS8182Q36BD-167I Datasheet HTML 7Page - GSI Technology GS8182Q36BD-167I Datasheet HTML 8Page - GSI Technology GS8182Q36BD-167I Datasheet HTML 9Page - GSI Technology GS8182Q36BD-167I Datasheet HTML 10Page - GSI Technology GS8182Q36BD-167I Datasheet HTML 11Page - GSI Technology GS8182Q36BD-167I Datasheet HTML 12Page - GSI Technology GS8182Q36BD-167I Datasheet HTML 13Page - GSI Technology GS8182Q36BD-167I Datasheet HTML 14Page - GSI Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 36 page
background image
GS8182Q08/09/18/36BD-333/300/250/200/167/133
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03d 11/2011
10/36
© 2007, GSI Technology
Special Functions
Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18
version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble
Write Enable” and “NBx” may be substituted in all the discussion above.
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time
BW0
BW1
D0–D8
D9–D17
Beat 1
0
1
Data In
Don’t Care
Beat 2
1
0
Don’t Care
Data In
Resulting Write Operation
Byte 1
D0–D8
Byte 2
D9–D17
Byte 3
D0–D8
Byte 4
D9–D17
Written
Unchanged
Unchanged
Written
Beat 1
Beat 2
Output Register Control
SigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output
Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the
output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K
and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to
function as a conventional pipelined read SRAM.


Codice articolo simile - GS8182Q36BD-167I

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
GSI Technology
GS8182Q36BGD-167 GSI-GS8182Q36BGD-167 Datasheet
738Kb / 36P
   18Mb SigmaQuad-IITM Burst of 2 SRAM
More results

Descrizione simile - GS8182Q36BD-167I

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
GSI Technology
GS8182Q18BD-300M GSI-GS8182Q18BD-300M Datasheet
446Kb / 35P
   18Mb SigmaQuad-IITM Burst of 2 SRAM
GS8182Q36BGD-167 GSI-GS8182Q36BGD-167 Datasheet
738Kb / 36P
   18Mb SigmaQuad-IITM Burst of 2 SRAM
GS8182Q09BD-200I GSI-GS8182Q09BD-200I Datasheet
738Kb / 36P
   18Mb SigmaQuad-IITM Burst of 2 SRAM
GS8182D09BGD-333 GSI-GS8182D09BGD-333 Datasheet
726Kb / 36P
   18Mb SigmaQuad-IITM Burst of 4 SRAM
GS8182D08BD-167I GSI-GS8182D08BD-167I Datasheet
726Kb / 36P
   18Mb SigmaQuad-IITM Burst of 4 SRAM
GS8180QV18BD-167 GSI-GS8180QV18BD-167 Datasheet
414Kb / 28P
   18Mb Burst of 2 SigmaQuad SRAM
GS8180QV18BD-200 GSI-GS8180QV18BD-200 Datasheet
414Kb / 28P
   18Mb Burst of 2 SigmaQuad SRAM
GS8180QV36BD-200I GSI-GS8180QV36BD-200I Datasheet
414Kb / 28P
   18Mb Burst of 2 SigmaQuad SRAM
GS8180QV18BD-200I GSI-GS8180QV18BD-200I Datasheet
414Kb / 28P
   18Mb Burst of 2 SigmaQuad SRAM
GS8180QV18BGD-167 GSI-GS8180QV18BGD-167 Datasheet
414Kb / 28P
   18Mb Burst of 2 SigmaQuad SRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36


Scheda tecnica Scarica

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEETIT.COM
Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com