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GS8182Q18BD-300M Scheda tecnica(PDF) 8 Page - GSI Technology |
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GS8182Q18BD-300M Scheda tecnica(HTML) 8 Page - GSI Technology |
8 / 35 page GS8182Q08/09/18/36BD-300M Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.00a 11/2011 8/35 © 2011, GSI Technology SigmaQuad-II B2 SRAM DDR Write The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of K. A low on the Write Enable-bar pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on the rising edge of K along with the write address. Clocking in a high on W causes a write port deselect cycle. SigmaQuad-II B2 Double Data Rate SRAM Write First Write A Read B Read C Write D NOP Read E Write F Read G Write H NOP A B C D E F G H A A+1 D D+1 F F+1 H H+1 A A+1 D D+1 F F+1 H H+1 B B+1 C C+1 E E+1 K K Address R W BWx D C C Q CQ CQ |
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