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RT5508 Scheda tecnica(PDF) 46 Page - Richtek Technology Corporation |
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RT5508 Scheda tecnica(HTML) 46 Page - Richtek Technology Corporation |
46 / 57 page RT5508 Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5508-01 March 2017 46 ADDR Byte Bits R/W Name Description Default 0x95 1 7 - Reserved - 6 R/W DAC_SEL 1 : RHP_DAC_EN only, 0 : RHP_DAC_EN + LHP_DAC_EN 0 5 R/W ADC_HPF_EN ADC high-pass filter enable 0 4 R/W ADC_CLK_INV Only for FPGA. Invert the ADC_CLK port 0 3 R/W D_OTP_TM_EN OTP test mode enable, change OTP Threshold level to 0 degree around 0 2:0 - Reserved - 2'b00 0x96 1 7 R/W ovp_prot_en OVP protection enable : 1 : enable ovp protection 0 : disable 0 6 R/W uvp_prot_en UVP protection eenable : 1 : enable uvp protection 0 : disable 0 5 R/W cd_ocp_prot_en Class-D OCP protection enable : 1 : enable class-d ocp protection 0 : disable 0 4:1 R/W gpwm_lv_reg[3:0] Digital GPWM setting for triangle Vp-p, 0000 : 0.5Vpp to 1111 : 1.1Vpp@30mVpp 4'h0 0 R/W gpwm_lv_source digital GPWM setting source : 0 : from digital state machine 1 : from register 0x96[4:1] 0 0x97 1 0 R/W PLL_FREERUN 1 : PLL free run mode 1'b1 0x9a 1 7 R/W bypass_vsettle Enable to bypass vref_settle for internal dcm_en 1 6 R/W bypass_il0 Enable to bypass iL0 for internal dcm_en 1 5:4 R/W PLL_BW_RATIO Kp / Ki ratio : 2'b00 -> Kp = 1; Ki = 1/8 2'b00 -> Kp = 1; Ki = 1/16 2'b00 -> Kp = 1; Ki = 1/32 2'b00 -> Kp = 1; Ki = 1/64 2'b01 3 R/W PLL_DZONE_MODE dead-zone mode: 1 : accumlate Kp path, larger BW. 0 : skip Ki path, smaller BW. 1'b1 2 R/W PLL_NDSM_MODE DSM order for fractional-N mode 0 : 1 st order 1 : 2 nd order 1'b1 1:0 R/W PLL_REF_DIV[1:0] Input reference frequency divided ratio 2'b00 -> FREF 2'b01 -> FREF/2 2'b10 -> FREF/4 2'b11 -> FREF/8 2'b00 |
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