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M-CAS-C8237 Scheda tecnica(PDF) 5 Page - Altera Corporation |
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M-CAS-C8237 Scheda tecnica(HTML) 5 Page - Altera Corporation |
5 / 5 page CAST, Inc. 11 Stonewall Court Woodcliff Lake, NJ 076747 USA tel 201-391-8300 fax 201-391-8694 Copyright © CAST, Inc. 2004, All Rights Reserved. Temporary Word Count Register (16 Bit Decrementor) It will decrement the word count after each transfer. When the value in the register goes from zero to FFFFH, a Terminal Count (TC) will be generated. Temporary Address Register (16 Bit Incremen- tor/Decrementor) Base on the mode of the address, the address will be decre- mented or incremented after each transfer. And the intermediate values of the address are stored in the Current Address register during the transfer. Implementation Results The following are typical performance and utilization results us- ing a variety of Altera devices. Supported Device Utilization Performance Family Tested LEs Memory Memory bits Fmax Cyclone EP1C20-6 1,007 0 0 97 MHz Stratix EP1S20-5 1,007 0 0 94 MHz Stratix-II EP2S60-3 816 0 0 140 MHz Support The core as delivered is warranted against defects for three years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Addi- tional maintenance and support options are available. Verification The core has been verified through extensive simulation and rigorous code coverage measurements. Deliverables The core includes everything required for successful implemen- tation: Encrypted Licenses • Post-synthesis EDIF netlist • Assignment & Configuration • Symbol file • Include file • Wrapper for matching the I/O of the original device • Vectors for testbench HDL Source Licenses • VHDL or Verilog RTL source code • Testbench • Wrapper for matching the I/O of the original device • Vectors for testbench • Expected results for testbench • Simulation and synthesis script Contents subject to change without notice. July 2003 |
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