Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

GS81302T08E-300 Scheda tecnica(PDF) 7 Page - GSI Technology

Il numero della parte GS81302T08E-300
Spiegazioni elettronici  144Mb SigmaDDRTM-II Burst of 2 SRAM
Download  36 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  GSI [GSI Technology]
Homepage  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS81302T08E-300 Scheda tecnica(HTML) 7 Page - GSI Technology

Back Button GS81302T08E-300 Datasheet HTML 3Page - GSI Technology GS81302T08E-300 Datasheet HTML 4Page - GSI Technology GS81302T08E-300 Datasheet HTML 5Page - GSI Technology GS81302T08E-300 Datasheet HTML 6Page - GSI Technology GS81302T08E-300 Datasheet HTML 7Page - GSI Technology GS81302T08E-300 Datasheet HTML 8Page - GSI Technology GS81302T08E-300 Datasheet HTML 9Page - GSI Technology GS81302T08E-300 Datasheet HTML 10Page - GSI Technology GS81302T08E-300 Datasheet HTML 11Page - GSI Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 36 page
background image
GS81302T08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03b 12/2011
7/35
© 2011, GSI Technology
Background
Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.
Therefore, the SigmaDDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are
unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed
Common I/O SRAM data bandwidth in half.
Burst Operations
Read and write operations are "burst" operations. In every case where a read or write command is accepted by the SRAM, it will
respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K, as illustrated in
the timing diagrams. This means that it is possible to load new addresses every K clock cycle. Addresses can be loaded less often,
if intervening deselect cycles are inserted.
Deselect Cycles
Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to
the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the two beat read data transfer
and then execute the deselect command, returning the output drivers to high-Z. A high on the LD pin prevents the RAM from
loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer
operations.
SigmaDDR-II Burst of 2 SRAM Read Cycles
The SRAM executes pipelined reads. The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The read
command (LD low and R/W high) is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the SRAM
produces data out in response to the next rising edge of C (or the next rising edge of K, if C and C are tied high). The second beat
of data is transferred on the next rising edge of C, for a total of two transfers per address load.
SigmaDDR-II Burst of 2 SRAM Write Cycles
The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The SRAM executes "late write" data transfers.
Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write command
(LD and R/W low) and the write address. To complete the remaining beat of the burst of two write transfer, the SRAM captures
data in on the next rising edge of K, for a total of two transfers per address load.


Codice articolo simile - GS81302T08E-300

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
GSI Technology
GS81302T06 GSI-GS81302T06 Datasheet
390Kb / 29P
   144Mb SigmaDDRTM-II Burst of 2 SRAM
GS81302T07 GSI-GS81302T07 Datasheet
441Kb / 31P
   144Mb SigmaDDRTM-II Burst of 2 SRAM
More results

Descrizione simile - GS81302T08E-300

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
GSI Technology
GS81302TT07 GSI-GS81302TT07 Datasheet
436Kb / 30P
   144Mb SigmaDDRTM-II Burst of 2 SRAM
GS81302T06 GSI-GS81302T06 Datasheet
390Kb / 29P
   144Mb SigmaDDRTM-II Burst of 2 SRAM
GS81302T07 GSI-GS81302T07 Datasheet
441Kb / 31P
   144Mb SigmaDDRTM-II Burst of 2 SRAM
GS81302TT06 GSI-GS81302TT06 Datasheet
399Kb / 29P
   144Mb SigmaDDRTM-II Burst of 2 SRAM
GS81302R08 GSI-GS81302R08 Datasheet
1Mb / 35P
   144Mb SigmaDDRTM-II Burst of 4 SRAM
GS8662TT20 GSI-GS8662TT20 Datasheet
443Kb / 31P
   72Mb SigmaDDRTM-II Burst of 2 SRAM
GS81302Q18GE-300I GSI-GS81302Q18GE-300I Datasheet
372Kb / 34P
   144Mb SigmaQuadTM-II Burst of 2 SRAM
GS81302Q08E-250I GSI-GS81302Q08E-250I Datasheet
640Kb / 33P
   144Mb SigmaQuadTM-II Burst of 2 SRAM
GS81302Q18AGD-333 GSI-GS81302Q18AGD-333 Datasheet
608Kb / 29P
   144Mb SigmaQuadTM-II Burst of 2 SRAM
GS81302Q18AGD-375I GSI-GS81302Q18AGD-375I Datasheet
608Kb / 29P
   144Mb SigmaQuadTM-II Burst of 2 SRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36


Scheda tecnica Scarica

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEETIT.COM
Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com