Synchronous Truth Table

Operation

Type

Address

CK

CKE

ADV

W Bx

G

ZZ

DQ

Notes

Read Cycle, Begin Burst

R

External

L-H

L

L

H

X

L

H

L

L

L

Q

Read Cycle, Continue Burst

B

Next

L-H

L

H

X

X

X

X

X

L

L

Q

1,10

NOP/Read, Begin Burst

R

External

L-H

L

L

H

X

L

H

L

H

L

High-Z

2

Dummy Read, Continue Burst

B

Next

L-H

L

H

X

X

X

X

X

H

L

High-Z

1,2,10

Write Cycle, Begin Burst

W

External

L-H

L

L

L

L

L

H

L

X

L

D

3

Write Abort, Begin Burst

D

None

L-H

L

L

L

H

L

H

L

X

L

High-Z

1

Write Cycle, Continue Burst

B

Next

L-H

L

H

X

L

X

X

X

X

L

D

1,3,10

Write Abort, Continue Burst

B

Next

L-H

L

H

X

H

X

X

X

X

L

Deselect Cycle, Power Down

D

None

L-H

L

L

X

X

H

X

X

X

L

High-Z

Deselect Cycle, Power Down

D

None

L-H

L

L

X

X

X

X

H

X

L

High-Z

Deselect Cycle, Power Down

D

None

L-H

L

L

X

X

X

L

X

X

L

High-Z

Deselect Cycle, Continue

D

None

L-H

L

H

X

X

X

X

X

X

L

High-Z

1

Sleep Mode

None

X

X

X

X

X

X

X

X

X

H

High-Z

Clock Edge Ignore, Stall

Current

L-H

H

X

X

X

X

X

X

X

L

-

4

Notes:

1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect

cycle is executed first.

2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is

sampled low but no Byte Write pins are active so no write operation is performed.

3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write

cycles.

4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus

will remain in High Z.

5.

X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals

are Low

6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.

7. Wait states can be inserted by setting CKE high.

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

GS8160Z18/36DGT-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.03a 9/2013

7/22

© 2011, GSI Technology