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SN74AUP1G80DSF Scheda tecnica(PDF) 3 Page - Texas Instruments |
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SN74AUP1G80DSF Scheda tecnica(HTML) 3 Page - Texas Instruments |
3 / 38 page Q VCC CLK D GND 1 2 C B A Not to scale GND Q CLK D VCC 1 2 C B A Not to scale GND Q CLK N.C. D VCC GND Q 3 4 CLK 2 5 D 6 1 N.C. V CC CLK NC D 6 5 4 2 3 GND Q V CC 1 5 1 V CC D 2 CLK 3 4 GND Q 2 CLK 3 4 GND V CC 5 D Q 1 3 SN74AUP1G80 www.ti.com SCES593F – JULY 2004 – REVISED JULY 2017 Product Folder Links: SN74AUP1G80 Submit Documentation Feedback Copyright © 2004–2017, Texas Instruments Incorporated 5 Pin Configuration and Functions DBV Package 5-Pin SOT-23 Top View DCK Package 5-Pin SC70 Top View DRY Package 6-Pin SON Top View DSF Package 6-Pin SON Top View YFP Package 6-Pin DSBGA Bottom View YZP Package 5-Pin DSBGA Bottom View DPW Package(1) 5-Pin X2SON Top View (1) Preview only Pin Functions PIN I/O DESCRIPTION NAME DBV, DCK DRY, DSF YFP YZP DPW D 1 1 A1 A1 1 I Data input CLK 2 2 B1 B1 2 I Positive-Edge-Triggered Clock input GND 3 3 C1 C1 3 — Ground pin Q 4 4 C2 C2 4 O Inverted output NC — 5 B2 — — — No Internal Connection VCC 5 6 A2 A2 5 — Positive Supply |
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