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DAC08GBC Scheda tecnica(PDF) 5 Page - Analog Devices |
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DAC08GBC Scheda tecnica(HTML) 5 Page - Analog Devices |
5 / 12 page REV. B DAC08 –5– DAC08N DAC08G DAC08GR Parameter Symbol Conditions Limit Limit Limit Unit Resolution 8 8 8 Bits min Monotonicity 8 8 8 Bits min Nonlinearity NL ±0.1 ±0.19 ±0.39 % FS max Output Voltage VOC Full-Scale Current +18 +18 +18 V max Compliance Change < 1/2 LSB –10 –10 –10 V min Full-Scale Current IFS4 or VREF = 10.000 V 2.04 2.04 2.04 mA max IFS2 R14, R15 = 5.000 k Ω 1.94 1.94 1.94 mA min Full-Scale Symmetry IFSS ±8 ±8 ±16 µA max Zero-Scale Current IZS 24 4 µA max Output Current Range IFS1 or V– = –10 V, VREF = +15 V 2.1 2.1 2.1 mA min V– = –12 V, IFS2 VREF = +25 V 4.2 4.2 4.2 mA min R14, R15 = 5.000 k Ω Logic Input “0” VIL 0.8 0.8 0.8 V max Logic Input “1” VIH 22 2 V min Logic Input Current VLC = 0 V Logic “0” IIL VIN = –10 V to +0.8 V ±10 ±10 ±10 µA max Logic “1” IIH VIN = +2.0 V to +18 V ±10 ±10 ±10 µA max Logic Input Swing VIS V– = –15 V +18 +18 +18 V max –10 –10 –10 V min Reference Bias Current I15 –3 –3 –3 µA max Power Supply PSSIFS+ V+ = +4.5 V to +18 V 0.01 0.01 0.01 % FS/% V max Sensitivity PSSIFS– V– = –4.5 V to –18 V IREF = 1.0 mA Power Supply Current I+ VS = ±15 V 3.8 3.8 3.8 mA max IREF ≤ 2.0 mA –7.8 –7.8 –7.8 µA max Power Dissipation PD VS = ±15 V 174 174 174 mW max IREF ≤ 2.0 mA NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. (@ VS = 15 V, IREF = 2.0 mA; TA = 25 C, unless otherwise noted. Output characteristics apply to both IOUT and IOUT.) WAFER TEST LIMITS |
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