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CDCV855PW Scheda tecnica(PDF) 4 Page - Texas Instruments

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Il numero della parte CDCV855PW
Spiegazioni elettronici  2.5-V PHASE-LOCK LOOP CLOCK DRIVER
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
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CDCV855PW Scheda tecnica(HTML) 4 Page - Texas Instruments

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CDCV855, CDCV855I
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
VIK
Input voltage
All inputs
VDDQ = 2.3 V,
II = –18 mA
–1.2
V
V
High level output voltage
VDDQ = min to max, IOH = –1 mA
VDDQ – 0.1
V
VOH
High-level output voltage
VDDQ = 2.3 V,
IOH = –12 mA
1.7
V
V
Low level output voltage
VDDQ = min to max, IOL = 1 mA
0.1
V
VOL
Low-level output voltage
VDDQ = 2.3 V,
IOL = 12 mA
0.6
V
IOH
High-level output current
VDDQ = 2.3 V,
VO = 1 V
–18
–32
mA
IOL
Low-level output current
VDDQ = 2.3 V,
VO = 1.2 V
26
35
mA
VOD
Output voltage swing
Differential outputs are terminated with
1.1
VDDQ – 0.4
VOX
Output differential
cross-voltage}
Differential outputs are terminated with
120
VDDQ/2 – 0.2 VDDQ/2 VDDQ/2 + 0.2
V
II
Input current
VDDQ = 2.7 V,
VI = 0 V to 2.7 V
±10
µA
IOZ
High-impedance-state output
current
VDDQ = 2.7 V,
VO = VDDQ or GND
±10
µA
IDD(PD)
Power-down current on
VDDQ + AVDD
CLK and CLK = 0 MHz; PWRDWN = Low;
Σ of IDD and AIDD
100
200
µA
I
Dynamic current on V
Differential outputs
are terminated with
120
Ω / CL = 14 pF
f
167 MHz
150
180
mA
IDD
Dynamic current on VDDQ
Differential outputs
are terminated with
120
Ω / CL = 0 pF
fO = 167 MHz
130
160
mA
AIDD
Supply current on AVDD
fO = 167 MHz
8
10
mA
CI
Input capacitance
VDDQ = 2.5 V
VI = VDDQ or GND
2
2.5
3
pF
CO
Output capacitance
VDDQ = 2.5 V
VO = VDDQ or GND
2.5
3
3.5
pF
† All typical values are at respective nominal VDDQ.
‡ Differential cross-point voltage is expected to track variation of VDDQ and is the voltage at which the differential signals must be crossing.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
MIN
MAX
UNIT
fCLK
Operating clock frequency
60
180
MHz
Input clock duty cycle
40%
60%
Stabilization time (PLL mode)W
10
µs
Stabilization time (Bypass mode)w
30
ns
§ Recovery time required when the device goes from power-down mode into bypass mode (test mode with AVDD at GND).
¶ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.


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