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AM27C256-55JC Scheda tecnica(PDF) 10 Page - Advanced Micro Devices |
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AM27C256-55JC Scheda tecnica(HTML) 10 Page - Advanced Micro Devices |
10 / 12 page AMD 2-41 Am27C256 CAPACITANCE Parameter Parameter Test Symbol Description Conditions Typ Max Typ Max Typ Max Typ Max Unit CIN Input Capacitance VIN = 0 8 12 8 12 6 10 10 12 pF COUT Output Capacitance VOUT = 0 8 12 8 12 8 10 12 14 pF Notes: 1. This parameter is only sampled and not 100% tested. 2. TA = +25 °C, f = 1 MHz. CDV028 PL 032 PD 028 TS 032 SWITCHING CHARACTERISTICS over operating range unless otherwise specified (Notes 1, 3 and 4) Parameter Test JEDEC Standard Description Conditions -55 -70 -90 -120 -150 -200 -255 Unit tAVQV tACC Address to CE = OE = Min – – – – – – – Output Delay VIL Max 55 70 90 120 150 200 250 ns tELQV tCE Chip Enable to OE = VIL Min – – – – – – – Output Delay Max 55 70 90 120 150 200 250 ns tGLQV tOE Output Enable to CE = VIL Min – – – – – – – Output Delay Max 35 40 40 50 50 50 50 ns tEHQZ, tDF Min – – – – – – – tGHQZ (Note 2) Max 25 25 25 30 30 30 30 ns tAXQX tOH Min 0 0 0 0 0 0 0 Max – – – – – – – ns Parameter Symbols Am27C256 Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 2. This parameter is only sampled and not 100% tested. 3. Caution: The Am27C256 must not be removed from (or inserted into) a socket or board when VPP or VCC is applied. 4. For the -55 and -70: Output Load: 1 TTL gate and CL = 30 pF Input Rise and Fall Times: 20 ns Input Pulse Levels: 0 V to 3 V Timing Measurement Reference Level: 1.5 V for inputs and outputs For all other versions: Output Load: 1 TTL gate and CL = 100 pF Input Rise and Fall Times: 20 ns Input Pulse Levels: 0.45 V to 2.4 V Timing Measurement Reference Level: 0.8 V and 2 V inputs and outputs Chip Enable HIGH or Output Enable HIGH, whichever comes first, to Output Float Output Hold from Addresses, CE, or OE, whichever occurred first |
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