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ADC-318A Scheda tecnica(PDF) 3 Page - List of Unclassifed Manufacturers |
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ADC-318A Scheda tecnica(HTML) 3 Page - List of Unclassifed Manufacturers |
3 / 8 page ADC-318, ADC-318A 3 ® ® 318A requires that the characteristic impedance of all input/ output logic and analog input lines be properly matched. 2. Power supply lines and grounding may effect the perfor- mance of the ADC-318 and ADC-318A. Separate and substantial AGND and DGND ground planes are required. These grounds have to be connected to one earth point underneath the device. There are three digital grounds, DGND1 (pin 29), DGND2 (pins 20, 32, 41) and DGND3 (pin 12). These DGND 's are separated internally. DGND1 and DGND2 are always connected externally but DGND3 shall be connected differently depending on whether the single or dual power supply mode is used, as explained later. The ADC-318 and ADC-318A have separate +AVs and +DVs pins. It is recommended that both +AVs and +DVs be powered from a single source. Other external digital circuits must be powered with a separate +DVs. Layouts of +AVs and +DVs lines must be separated like the GND lines to avoid mutual interference and are connected to a point through an LC filter. There are two digital supplies +DVs1 (pin 30) and +DVs2 (pins 19, 31, 42). These are also separated internally. These must be tied together outside while in use. Bypassing all power lines with a 0.1uF ceramic chip capacitor and the use of multilayered PC boards is recommended. 3. The analog input terminal (pin 6) has 21pF of input capaci- tance. The input signal has to be given via a buffer amplifier which has enough driving power. Make lead wires as short as possible and use chip resistors and capacitors to avoid parasitic capacitance and inductance. 4. The use of a buffer amplifier and bypass capacitors is also recommended on the reference input terminals VRT (pin 11) and VRB (pin 2). The analog input range is determined by POWER REQUIREMENTS (cont.) Power Dissipation ADC-318 680 780 980 mW ADC-318A 570 790 960 mW PARAMETERS Operating Temp. Range, Case ADC-318, 318A –20 — +75 °C Thermal Impedance θja — 62.5 — °C/Watt Storage Temperature Range –65 — +150 °C Package Type 48-pin, plastic QFP Weight 0.25 ounces (0.7 grams) Footnotes: VIN = +3V +0.07Vrms VIH = DGND3–0.8V VIL = DGND3–1.6V VIH = 3.5V VIL = 0.2V TTL, 0.8 to 2.0V, CL = 5pF DMUX Mode, CL = 5pF; FC = Clock frequency Straight Mode, CL = 5pF CL = 5pF VIN = FS, DMUX mode VIN = FS, DMUX mode, Error >16LSB VIN = FS, Straight mode, Error >16LSB "Times Per Sample" Mounted on 50x50mm, 1.6mm thick glass fiber base epoxy board TECHNICAL NOTES 1. The ADC-318 and ADC-318A are ultra high speed full flash A/D converters that have 120MHz and 140MHz sampling rates respectively. The ADC-318 and ADC-318A are fully interchangeable products with the exception of their sampling rates. Their inputs are TTL, ECL and PECL compatible and their outputs are TTL compatible. Obtaining fully specified performance from the ADC-318 and ADC- 1 2 11 12 Figure 2-1: One Power Supply Operation (TTL, PECL) Figure 2-2: Two Power Supply Operation (ECL) Note: All capacitors not otherwise designated are 0.1µF + + + + 5V(A) 10µF 10µH 5V(D) 10µF 8 5 19 30 31 42 10µF 2 VRB +2V ANALOG IN +2V to +4V 4 6 7 9 11 VRT +4V 10µF A/D CLOCK 15 13 14 48 47 46 3 10 20 29 32 41 45 44 43 TTL CLOCK OUT 5V(D) 28 B BIT 1 27 B BIT 2 26 B BIT 3 25 B BIT 4 24 B BIT 5 23 B BIT 6 22 B BIT 7 21 B BIT 8 LSB MSB 40 A BIT 1 39 A BIT 2 38 A BIT 3 37 A BIT 4 36 A BIT 5 35 A BIT 6 34 A BIT 7 33 A BIT 8 LSB MSB ADC-318 12 1 TTL PECL ADC-318A 5V(D) + + + + + 5V(A) 10µF 10µH 5V(D) 10µF 8 5 19 30 31 42 10µF 2 VRB +2V ANALOG IN +2V to +4V 4 6 7 9 11 VRT +4V 10µF ECL A/D CLOCK A/D CLOCK 15 13 14 48 47 46 3 10 1 12 20 29 32 41 10µF 5V(D) 45 44 43 TTL CLOCK OUT 28 B BIT 1 27 B BIT 2 26 B BIT 3 25 B BIT 4 24 B BIT 5 23 B BIT 6 22 B BIT 7 21 B BIT 8 LSB MSB 40 A BIT 1 39 A BIT 2 38 A BIT 3 37 A BIT 4 36 A BIT 5 35 A BIT 6 34 A BIT 7 33 A BIT 8 LSB MSB ADC-318 ADC-318A 5V(D) 5V(D) |
Codice articolo simile - ADC-318A |
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Descrizione simile - ADC-318A |
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