ADC1031 datasheet(10/18 Pages) NSC

Il numero della parte	ADC1031

Spiegazioni elettronici	ADC1031/ADC1034/ADC1038 10-Bit Serial I/O A/D Converters with Analog Multiplexer and Track/Hold Function

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Produttore elettronici	NSC [National Semiconductor (TI)]

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10 Pin Descriptions

CCLK

The clock applied to this input controls the suc-

cessive approximation conversion time interval

The clock frequency applied to this input can be

between 700 kHz and 4 MHz

SCLK

The serial data clock input The clock applied to

this input controls the rate at which the serial

data exchange occurs and the analog sampling

time available to acquire an analog input voltage

The rising edge loads the information on the DI

pin into the multiplexer address shift register (ad-

dress register)

This address controls which

channel of the analog input multiplexer (MUX) is

selected

The falling edge shifts the data resulting from the

previous AD conversion out on DO CS and OE

enable or disable the above functions

DI

The serial data input pin The data applied to this

pin is shifted by SCLK into the multiplexer ad-

dress register The first 3 bits of data (A0 – A2)

are the MUX channel address (see the Multiplex-

er AddressChannel Assignment tables)

The

fourth bit (RL) determines the data format of the

conversion result in the conversion to be started

When RL is low the output data format is left-

justified when high it is right-justified When right-

justified six leading ‘‘0’’s are output on DO be-

fore the MSB information thus the complete con-

version result is shifted out in 16 clock periods

DO

The data output pin The AD conversion result

(D0 – D9) is output on this pin This result can be

left- or right-justified depending on the value of

RL bit shifted in on DI

SARS

This pin is an output and indicates the status of

the internal successive approximation register

(SAR) When high it signals that the AD conver-

sion is in progress This pin is set high after the

analog input sampling time (tCA) and remains

high for 41 CCLK periods When SARS goes low

the output shift register has been loaded with the

conversion result and another AD conversion

sequence can be started

CS

The chip select pin When a low is applied to this

pin the rising edge of SCLK shifts the data on DI

into the address register In the ADC1031 this pin

also functions as the OE pin

OE

The output enable pin When OE and CS are

both low the falling edge of SCLK shifts out the

previous AD conversion data on the DO pin

CH0 –

The analog inputs of the MUX A channel input is

CH7

selected by the address information at the DI pin

which is loaded on the rising edge of SCLK into

the address register

Source impedances (RS) driving these inputs

should be kept below 1 kX IfRS is greater than

1kX the sampled data comparator will not have

enough time to acquire the correct value of the

applied input voltage

The voltage applied to these inputs should not

exceed VCC or go below DGND or AGND by

more than 50 mV Exceeding this range on an

unselected channel will corrupt the reading of a

selected channel

VREFa

The positive analog voltage reference for the an-

alog inputs In order to maintain accuracy the

voltage range of VREF (VREF e VREFa b

VREFb) is 25 VDC to 50 VDC and the voltage at

VREFa cannot exceed VCC a 50 mV In the

ADC1031 VREFb is always GND

VREFb

The negative voltage reference for the analog in-

puts In order to maintain accuracy the voltage at

this pin must not go below DGND and AGND by

more than 50 mV or exceed 40% of VCC (for VCC

e

5V VREFb (max) e 2V) In the ADC1031

VREFb is internally connected to the GND pin

VCC

The power supply pin The operating voltage

range of VCC is 475 VDC to 525 VDC VCC

should be bypassed with 10 mF and 01 mF ca-

pacitors to digital ground for proper operation of

the AD converter

DGND

The digital and analog ground pins for the

AGND

ADC1034 and the ADC1038 In order to maintain

accuracy the voltage difference between these

two pins must not exceed 300 mV

GND

The digital and analog ground pin for the

ADC1031

20 Functional Description

21 DIGITAL INTERFACE

The ADC1034 and ADC1038 implement their serial inter-

face via seven digital control lines There are two clock in-

puts for the ADC1034ADC1038 The SCLK controls the

rate at which the serial data exchange occurs and the dura-

tion of the analog sampling time window The CCLK controls

the conversion time and must be continuously enabled A

low on CS enables the rising edge of SCLK to shift in the

serial multiplexer addressing data on the DI pin The first

three bits of this data select the analog input channel for the

ADC1038 and the ADC1034 (see the Channel Addressing

Tables) The following bit RL selects the output data for-

mat (right-justified or left-justified) for the conversion to be

started With CS and OE low the DO pin is active (out of

TRI-STATE) and the falling edge of SCLK shifts out the data

from the previous analog conversion When the first conver-

sion is started the data shifted out on DO is erroneous as it

depends on the state of the Parallel Load 16-Bit Shift Regis-

ter on power up which is unpredictable

The ADC1031 implements its serial interface with only four

control pins since it has only one analog input and comes in

an eight pin mini-dip package The SCLK CCLK CS and DO

pins are available for the serial interface The output data

format cannot be selected and defaults to a left-justified

format The state of DO is controlled by CS only

22 OUTPUT DATA FORMAT

When RL is low the output data format is left-justified

when high it is right-justified When right-justified six leading

‘‘0’’s are output on DO before the MSB and the complete

conversion result is shifted out in 16 clock periods

230 CS HIGH DURING CONVERSION

With a continuous SCLK input CS must be used to synchro-

nize the serial data exchange A valid CS is recognized if it

occurs at least 100 ns (tSET-UP) before the rising edge of

SCLK thus causing data to be input on DI If this does not

10

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