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74LVC3G14 Scheda tecnica(PDF) 1 Page - NXP Semiconductors |
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74LVC3G14 Scheda tecnica(HTML) 1 Page - NXP Semiconductors |
1 / 17 page 1. General description The 74LVC3G14 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL-families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as translator in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC3G14 provides three inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. 2. Features s Wide supply voltage range from 1.65 V to 5.5 V s 5 V tolerant input/output for interfacing with 5 V logic s High noise immunity s ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s ±24 mA output drive (V CC = 3.0 V) s CMOS low power consumption s Latch-up performance exceeds 250 mA s Direct interface with TTL levels s Multiple package options s Specified from −40 °C to +85 °C and −40 °C to +125 °C. 3. Applications s Wave and pulse shaper for highly noisy environment s Astable multivibrator s Monostable multivibrator. 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 03 — 31 January 2005 Product data sheet |
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