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AD9261BCPZRL7-10 Scheda tecnica(PDF) 5 Page - Analog Devices |
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AD9261BCPZRL7-10 Scheda tecnica(HTML) 5 Page - Analog Devices |
5 / 29 page AD9261 Rev. 0 | Page 4 of 28 AC SPECIFICATIONS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS, unless otherwise noted. Table 2. Parameter1 Temp Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz Full 81 83 dB fIN = 4.2 MHz 25°C 83 dB fIN = 8.4 MHz 25°C 83 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz 25°C 13.5 Bits fIN = 4.2 MHz 25°C 13.5 Bits fIN = 8.4 MHz 25°C 13.5 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz Full 87 80 dBc fIN = 4.2 MHz 25°C 87 dBc fIN = 8.4 MHz 25°C <120 dBc NOISE SPECTRAL DENSITY (NSD) AIN= −2 dBFS Full −155 −153 dB/Hz AIN = −40 dBFS Full −156 −154.5 dB/Hz NOISE FIGURE2 25°C 15 dB TWO-TONE SFDR fIN1 = 2.1 MHz at −8 dBFS, fIN2 = 2.4 MHz at −8 dBFS 25°C 93 dBc fIN1 = 3.6 MHz at −8 dBFS, fIN2 = 4.2 MHz at −8 dBFS 25°C 92.5 dBc fIN1 = 7.2 MHz at −8 dBFS, fIN2 = 8.4 MHz at −8 dBFS 25°C 92.5 dBc ANALOG INPUT BANDWIDTH 25°C 10 MHz APERTURE JITTER 25°C 1 ps rms 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Noise figure with respect to 50 Ω. AD9261 internal impedance is 1000 Ω differential. See the AN-835 Application Note for a definition. DIGITAL DECIMATION FILTERING CHARACTERISTICS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, unless otherwise noted. Table 3. 2.5 MHz BW 5 MHZ BW 10 MHz BW Parameter1 Min Typ Max Min Typ Max Min Typ Max Unit Pass-Band Transition 2.5 3.75 5 6.5 10 13 MHz Pass-Band Ripple <0.1 <0.1 <0.1 dB Stop Band 3.75 MHz − fS/2 6.5 MHz − fS/2 13 MHz − fS/2 MHz Stop Band Attenuation >85 >85 >85 dB 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. |
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