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AD7607BSTZ-RL Scheda tecnica(PDF) 9 Page - Analog Devices

Il numero della parte AD7607BSTZ-RL
Spiegazioni elettronici  8-Channel DAS with 14-Bit, Bipolar Input, Simultaneous Sampling ADC
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD7607BSTZ-RL Scheda tecnica(HTML) 9 Page - Analog Devices

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AD7607
Data Sheet
Rev. C | Page 8 of 32
Limit at TMIN, TMAX
Parameter
Min
Typ
Max
Unit
Description
t27
Delay from RD falling edge to FRSTDATA low
19
ns
VDRIVE = 3.3 V to 5.25 V
24
ns
VDRIVE = 2.3 V to 2.7 V
t28
Delay from 16th SCLK falling edge to FRSTDATA low
17
ns
VDRIVE = 3.3 V to 5.25 V
22
ns
VDRIVE = 2.3 V to 2.7 V
t29
24
ns
Delay from CS rising edge until FRSTDATA three-state enabled
1
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
2
The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <3 LSB performance matching between channel sets.
3
A buffer, which is equivalent to a load of 20 pF on the output pins, is used on the data output pins for these measurements.
Timing Diagrams
tCYCLE
t3
t5
t2
t4
t1
t7
tRESET
tCONV
CONVST A,
CONVST B
CONVST A,
CONVST B
BUSY
CS
RESET
Figure 2. CONVST Timing—Reading After a Conversion
tCYCLE
t3
t5
t6
t2
t1
tCONV
CONVST A,
CONVST B
CONVST A,
CONVST B
BUSY
CS
t7
tRESET
RESET
Figure 3. CONVST Timing—Reading During a Conversion
DATA:
DB[15:0]
FRSTDATA
CS
RD
INVALID
V1
V2
V3
V7
V8
V4
t10
t8
t13
t24
t26
t27
t14
t11
t15
t9
t16
t17
t29
Figure 4. Parallel Mode, Separate CS and RD Pulses


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