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KAT1108E Scheda tecnica(PDF) 7 Page - Integrated Device Technology |
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KAT1108E Scheda tecnica(HTML) 7 Page - Integrated Device Technology |
7 / 22 page 6 Bit Digital Step Attenuator 1 MHz to 4000 MHz Glitch-FreeTM, Digital Step Attenuator 7 Rev 1, May 2017 IDTF1912NCGI Datasheet Figure 2 - Serial Register Timing Diagram Note - When Latch enable is high, the shift register is disabled and DATA is NOT continuously clocked into the shift register which minimizes noise. It is recommended that Latch enable be left high when the device is not being programmed. Table 3 - Serial Mode Timing Table Interval Symbol Description Min Spec Max Spec Units tmc Parallel to Serial Setup Time - From rising edge of VMODE to rising edge of CLK for D5 100 ns tds Clock high pulse width 10 ns tcls LE Setup Time - From the rising edge of CLK pulse for D0 to LE rising edge minus half the clock period. 10 ns tlew LE pulse width 30 ns tdsc Data Setup Time - From the starting edge of Data bit to rising edge of CLK 10 ns Tdht Data Hold Time - From rising edge of CLK to falling edge of the Data bit. 10 ns |
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