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TP3071J Scheda tecnica(PDF) 3 Page - National Semiconductor (TI) |
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TP3071J Scheda tecnica(HTML) 3 Page - National Semiconductor (TI) |
3 / 26 page Pin Descriptions (Continued) Pin Description FS R Receive Frame Sync input. Normally a pulse or squarewave with an 8 kHz repetition rate is applied to this input to define the start of the receive time slot assigned to this device (non-delayed data timing mode), or the start of the receive frame (delayed data timing mode using the internal time-slot assignment counter). BCLK Bit clock input used to shift PCM data into and out of the D R and DX pins. BCLK may vary from 64 kHz to 4.096 MHz in 8 kHz increments, and must be synchronous with MCLK. MCLK Master clock input used by the switched capacitor filters and the encoder and decoder sequencing logic. Must be 512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz or 4.096 MHz and synchronous with BCLK. VF XI The Transmit analog high-impedance input. Voice frequency signals present on this input are encoded as an A-law or µ-law PCM bit stream and shifted out on the selected D X pin. VF RO The Receive analog power amplifier output, capable of driving load impedances as low as 300 Ω (depending on the peak overload level required). PCM data received on the assigned D R pin is decoded and appears at this output as voice frequency signals. D X0 D X1 D X1 is available on the TP3070 only; DX0is available on all devices. These Transmit Data TRI-STATE® outputs remain in the high impedance state except during the assigned transmit time slot on the assigned port, during which the transmit PCM data byte is shifted out on the rising edges of BCLK. TS X0 TS X1 TS X1 is available on the TP3070 only; TSX0is available on all devices. Normally these open-drain outputs are floating in a high impedance state except when a time-slot is active on one of the D X outputs, when the appropriate TS X output pulls low to enable a backplane line-driver. D R0 D R1 D R1 is available on the TP3070 only; DR0is available on all devices. These receive data inputs are inactive except during the assigned receive time slot of the assigned port when the receive PCM data is shifted in on the falling edges of BCLK. CCLK Control Clock input. This clock shifts serial control information into or out from CI/O or CI and CO when the CS input is low, depending on the current instruction. CCLK may be asynchronous with the other system clocks. Pin Description CI/O This is the Control Data I/O pin which is provided on the TP3071. Serial control information is shifted to or read from COMBO II on this pin when CS is low. The direction of the data is determined by the current instruction as defined in Table 1. CI This is a separate Control Input, available only on the TP3070. It can be connected to CO if required. CO This is a separate Control Output, available only on the TP3070. It can be connected to CI if required. CS Chip Select input. When this pin is low, control information can be written to or read from COMBO II via the CI/O pin (or CI and CO). IL5–IL0 IL5 through IL0 are available on the TP3070. IL4 through IL0 are available on the TP3071. Each Interface Latch I/O pin may be individually programmed as an input or an output determined by the state of the corresponding bit in the Latch Direction Register (LDR). For pins configured as inputs, the logic state sensed on each input is latched into the Interface Latch Register (ILR) whenever control data is written to COMBO II, while CS is low, and the information is shifted out on the CO (or CI/O) pin. When configured as outputs, control data written into the ILR appears at the corresponding IL pins. MR This logic input must be pulled low for normal operation of COMBO II. When pulled momentarily high (at least 1 µsec.), all programmable registers in the device are reset to the states specified under “Power-On Initialization”. NC No Connection. Do not connect to this pin. Do not route traces through this pin. Functional Description POWER-ON INITIALIZATION When power is first applied, power-on reset circuitry initial- izes the COMBO II and puts it into the power-down state. The gain control registers for the transmit and receive gain sections are programmed to OFF (00000000), the hybrid balance circuit is turned off, the power amp is disabled and the device is in the non-delayed timing mode. The Latch Di- rection Register (LDR) is pre-set with all IL pins programmed as inputs, placing the SLIC interface pins in a high imped- ance state. The CI/O pin is set as an input ready for the first control byte of the initialization sequence. Other initial states in the Control Register are indicated in Section 2.0. A reset to these same initial conditions may also be forced by driving the MR pin momentarily high. This may be done ei- ther when powered-up or down. For normal operation this pin must be pulled low. If not used, MR should be hard-wired to ground. The desired modes for all programmable functions may be initialized via the control port prior to a Power-up command. www.national.com 3 |
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