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SI5017-EVB Scheda tecnica(PDF) 1 Page - Silicon Laboratories |
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SI5017-EVB Scheda tecnica(HTML) 1 Page - Silicon Laboratories |
1 / 12 page Rev. 1.0 12/02 Copyright © 2002 by Silicon Laboratories Si5017-EVB-DS10 Si5017-EVB EVALUATION BOARD FOR Si5017 SiPHY™ SONET/SDH CLOCK AND DATA RECOVERY IC Description The Si5017 evaluation board provides a platform for testing and characterizing Silicon Laboratories’ Si5017 SiPHY™ SONET/SDH clock and data recovery IC. The Si5017 CDR supports OC-48, STM-16, and 2.7 Gbps FEC rates. All high-speed I/Os are ac coupled to ease interfacing to industry standard test equipment. Features Single 3.3 V power supply Differential I/Os ac coupled Simple jumper configuration Functional Block Diagram REFCLK + – Z C = 50 Ω Z C = 50 Ω Z C = 50 Ω Z C = 50 Ω DATAIN + – CLKOUT + – DATAOUT + – Z C = 50 Ω Z C = 50 Ω Z C = 50 Ω Z C = 50 Ω Pulse Generator Pattern Generator Jitter Analyzer Scope Pattern Analyzer Si5017 LOS LTR Si5017-EVB DSQLCH RESET/CAL CLKDSBL Jumpers REXT 10 k Ω Test Points LOL BER_ALM LOS_LVL SLICE_LVL BER_LVL Ω VDD 210 Ω 348 |
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