REV. 0

AD1991

–5–

PIN CONFIGURATION

52 51 50 49 48

43 42 41 40

47 46 45 44

14 15 16 17 18 19 20 21 22 23 24 25 26

1

2

3

4

5

6

7

8

9

10

11

13

12

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

39

38

37

36

35

34

33

32

31

30

29

28

27

AD1991

PGND1

OUTA

PGND1

PGND1

PGND1

PGND2

PGND2

PGND2

PGND2

OUTA

OUTA

OUTB

OUTB

OUTB

OUTC

OUTC

OUTC

OUTD

OUTD

OUTD

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic In/Out

Description

1

PGND1

Negative power supply for high power Transistors A2 and B2.

2, 3, 4

OUTA

O

Output of transistor pair A1 and A2.

5, 6, 7

Positive power supply for high power Transistors A1 and B1.

8, 9, 10

OUTB

O

Output of transistor pair B1 and B2.

11, 12, 13

PGND1

Negative power supply for high power Transistors A2 and B2.

14

ERR3

I/O

Edge speed setting MSB during RESET/active low thermal shutdown error output during

normal operation.

15

ERR2

I/O

Edge speed setting Bit 1 during RESET/active low thermal warning error output during

normal operation.

16

ERR1

I/O

Nonoverlap time setting MSB during RESET/active thermal low shutdown error output

during normal operation.

17

ERR0

I/O

Nonoverlap time setting Bit 1 during RESET/active low data-loss error output or low-side

transistor disable input during normal operation.

18

INA

I

Control pin for Transistors A1 and A2 always; also control pin for B1 and B2 in 2-channel mode.

19

INB

I

Edge speed setting LSB during RESET/during normal operation, control pin for Transistors

B1 and B2 in 4-channel mode; no function in 2-channel mode.

20

Positive power supply for low power digital circuitry.

21

DGND

Negative power supply for low power digital circuitry.

22

MUTE

I

Active low clickless mute input.

23

INC

I

Control pin for Transistors C1 and C2 always; also control pin for D1 and D2 in 2-channel mode.

24

IND

I

Nonoverlap time setting LSB during RESET/during normal operation, control pin for Transis-

tors D1 and D2 in 4-channel mode; no function in 2-channel mode.

25

RST/PDN

I

Active low RESET/power-down input.

26

CLK

I

External clock input in external clock mode.

27, 28, 29

PGND2

Negative power supply for high power Transistors C2 and D2.

30, 31, 32

OUTD

O

Output of transistor pair D1 and D2.

33, 34, 35

Positive power supply for high power Transistors C1 and D1.

36, 37, 38

OUTC

O

Output of transistor pair C1 and C2.

39, 40, 41, 42

PGND2

Negative power supply for high power Transistors C2 and D2.

43, 45, 48, 49

AGND

Negative power supply for low power analog circuitry.

44

MODE0

Clock source select (referenced to AGND); normally connected to AGND.

46

Positive power supply for low power analog circuitry.

47

MODE1

I

Channel mode select (referenced to AGND).

50, 51, 52

PGND1

Negative power supply for high power Transistors A2 and B2.