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TPA6111A2DG4 Scheda tecnica(PDF) 4 Page - Texas Instruments |
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TPA6111A2DG4 Scheda tecnica(HTML) 4 Page - Texas Instruments |
4 / 29 page 4 TPA6111A2 SLOS313C – DECEMBER 2000 – REVISED MARCH 2016 www.ti.com Product Folder Links: TPA6111A2 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500 7.3 Recommended Operating Conditions MIN MAX UNIT VDD Supply voltage 2.5 5.5 V TA Operating free-air temperature –40 85 °C VIH High-level input voltage (SHUTDOWN) 60% × VDD V VIL Low-level input voltage (SHUTDOWN) 25% × VDD V (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.4 Thermal Information THERMAL METRIC(1) TPA6111A2 UNIT D (SOIC) DGN (MSOP) 8 PINS 8 PINS RθJA Junction-to-ambient thermal resistance 114.7 55.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 59.0 47.3 °C/W RθJB Junction-to-board thermal resistance 54.9 36.4 °C/W ψJT Junction-to-top characterization parameter 14.2 2.3 °C/W ψJB Junction-to-board characterization parameter 54.4 36.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — 9.2 °C/W 7.5 DC Electrical Characteristics, VDD = 3.3 V at VDD = 3.3 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOO Output offset voltage 10 mV PSRR Power supply rejection ratio VDD = 3.2 V to 3.4 V 70 dB IDD Supply current SHUTDOWN (pin 5) = 0 V 1.5 3 mA IDD(SD) Supply current in shutdown mode SHUTDOWN (pin 5) = VDD 1 10 µA Zi Input impedance > 1 M Ω 7.6 AC Operating Characteristics, VDD = 3.3 V VDD = 3.3 V, TA = 25°C, RL = 16 Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PO Output power (each channel) THD ≤ 0.1%, f = 1 kHz 60 mW THD+N Total harmonic distortion + noise PO = 40 mW, 20 Hz – 20 kHz 0.4% BOM Maximum output power BW G = 20 dB, THD < 5% > 20 kHz Phase margin Open-loop 96° Supply ripple rejection f = 1 kHz, C(BYP) = 0.47 µF 71 dB Channel/channel output separation f = 1 kHz, PO = 40 mW 89 dB SNR Signal-to-noise ratio PO = 50 mW, AV = 1 100 dB Vn Noise output voltage AV = 1 11 µV(rms) |
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