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DAC5682ZIRGC Scheda tecnica(PDF) 10 Page - Texas Instruments |
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DAC5682ZIRGC Scheda tecnica(HTML) 10 Page - Texas Instruments |
10 / 66 page DAC5682Z SLLS853F – AUGUST 2007 – REVISED JANUARY 2015 www.ti.com Electrical Characteristics — DC Specification (continued) over operating free-air temperature range , AVDD = 3.3 V, CLKVDD = 1.8 V, IOVDD = 3.3 V, DVDD = 1.8 V, IoutFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AVDD + IOVDD current, 3.3 V Mode 1: 2X2, PLL = OFF, CLKIN = 983.04 MHz 135 mA FDAC = 983.04 MHz, IF = 184.32 MHz DVDD + CLKVDD current, 1.8 V 450 mA DACA and DACB ON, 4 carrier WCDMA Power Dissipation 1255 mW AVDD + IOVDD current, 3.3 V Mode 2: 2X2, PLL = ON (8X), CLKIN = 122.88 145 mA MHz DVDD + CLKVDD current, 1.8 V 485 mA FDAC = 983.04 MHz, IF = 184.32 MHz 1350 Power Dissipation mW DACA and DACB ON, 4 carrier WCDMA AVDD + IOVDD current, 3.3 V Mode 3: 2X4, CMIX0 = Fs/4, PLL = OFF, CLKIN = 135 mA 983.04 MHz DVDD + CLKVDD current, 1.8 V 480 mA FDAC = 983.04 MHz, IF = 215.04 MHz 1310 Power Dissipation mW DACA and DACB ON, 4 carrier WCDMA P AVDD + IOVDD current, 3.3 V Mode 4: 2X4, CMIX0 = Fs/4, PLL = ON (8X), 145 mA CLKIN = 122.88 MHz DVDD + CLKVDD current, 1.8 V 505 mA FDAC = 983.04 MHz, IF = 215.04 MHz 1400 1600 Power Dissipation mW DACA and DACB ON, 4 carrier WCDMA AVDD + IOVDD current, 3.3 V Mode 5: 2X2, CMIX0 = Fs/4, PLL = OFF, CLKIN = 5 mA 983.04 MHz DVDD + CLKVDD current, 1.8 V 185 mA FDAC = 983.04 MHz, Digital Logic Disabled 350 Power Dissipation mW DACA and DACB SLEEP, Static Data Pattern AVDD + IOVDD current, 3.3 V Mode 6: 2X4, PLL = OFF, CLKIN = OFF 3.0 mA FDAC = OFF, Digital Logic Disabled DVDD + CLKVDD current, 1.8 V 4.0 mA DACA and DACB = SLEEP, Static Data Pattern Power Dissipation 17.0 30.0 mW PSRR Power supply rejection ratio DC tested –0.2 0.2 %FSR/V T Operating range –40 85 °C 7.6 Electrical Characteristics — AC Specification (1) Over recommended operating free-air temperature range, AVDD, IOVDD = 3.3 V, CLKVDD, DVDD = 1.8 V, IOUTFS = 20 mA, 4:1 transformer output termination, 50 Ω doubly terminated load (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT Maximum output update fCLK 1000 MSPS rate Output settling time to Transition: Code 0x0000 to 0xFFFF ts(DAC) 10.4 ns 0.1% tpd Output propagation delay 2.5 ns Output rise time 10% to tr(IOUT) 220 ps 90% Output fall time 90% to tf(IOUT) 220 ps 10% No interpolation, PLL Off 78 DAC Digital latency x2 interpolation, PLL Off 163 clock cycles x4 interpolation, PLL Off 308 IOUT current settling to 1% of IOUTFS. DAC wake-up time 80 Measured from SDENB; Register 0x06, toggle Bit 4 from 1 to 0. Power- μs up time IOUT current settling to 1% of IOUTFS. DAC sleep time 80 Measured from SDENB; Register 0x06, toggle Bit 4 from 0 to 1. (1) Measured single-ended into 50 Ω load. 10 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5682Z |
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