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DAC5682Z Scheda tecnica(PDF) 6 Page - Texas Instruments

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Il numero della parte DAC5682Z
Spiegazioni elettronici  16-Bit, 1.0 GSPS 2x-4x Interpolating Dual-Channel Digital-to-Analog Converter (DAC)
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Produttore elettronici  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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DAC5682Z
SLLS853F – AUGUST 2007 – REVISED JANUARY 2015
www.ti.com
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
8, 12, 14,
LVDS negative input data bits 0 through 15. (See D[15:0]P description above)
16, 18, 20,
D15N is most significant data bit (MSB) – pin 8
22, 24, 28,
D0N is least significant data bit (LSB) – pin 43
D[15..0]N
I
30, 32, 34,
36, 38, 41,
43
LVDS positive input clock. Unlike the other LVDS inputs, the DCLKP/N pair is self-biased to approximately
DVDD/2 and does not have an internal termination resistor in order to optimize operation of the DLL circuit.
DCLKP
25
I
See DLL Operation. For proper external termination, connect a 100
Ω resistor across LVDS clock source
lines followed by series 0.01
μF capacitors connected to each of DCLKP and DCLKN pins (see ). For best
performance, the resistor and capacitors should be placed as close as possible to these pins.
DCLKN
26
I
LVDS negative input clock. (See the DCLKP description)
10, 39, 50,
Digital supply voltage. (1.8 V)
DVDD
I
63
Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD).
EXTIO
56
I/O
Used as 1.2-V internal reference output when EXTLO = GND, requires a 0.1
μF decoupling capacitor to
AGND when used as reference output.
EXTLO
58
O
Connect to GND for internal reference, or AVDD for external reference.
4, Thermal
Pin 4 and the Thermal Pad located on the bottom of the QFN package is ground for AVDD, DVDD and
GND
I
Pad
IOVDD supplies.
A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full
scale current sink and the least positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data input results in
IOUTA1
52
O
a 0 mA current sink and the most positive voltage on the IOUTA1 pin. In single DAC mode, outputs appear
on the IOUTA1/A2 pair only.
A-Channel DAC complementary current output. The IOUTA2 has the opposite behavior of the IOUTA1
IOUTA2
53
O
described above. An input data value of 0x0000 results in a 0-mA sink and the most positive voltage on the
IOUTA2 pin.
IOUTB1
61
O
B-Channel DAC current output. See the IOUTA1 description above.
IOUTB2
60
O
B-Channel DAC complementary current output. See the IOUTA2 description above.
IOVDD
9
I
Digital I/O supply voltage (3.3 V) for pins RESETB, SCLK, SDENB, SDIO, SDO.
PLL loop filter connection. If not using the clock multiplying PLL, the LPF pin may be left open. Set both
LPF
64
I
PLL_bypass and PLL_sleep control bits for reduced power dissipation.
RESETB
49
I
Resets the chip when low. Internal pullup.
SCLK
47
I
Serial interface clock. Internal pulldown.
SDENB
48
I
Active low serial data enable, always an input to the DAC5682Z. Internal pullup.
Bi-directional serial interface data in 3-pin mode (default). In 4-pin interface mode (CONFIG5 sif4), the SDIO
SDIO
46
I/O
pin is an input only. Internal pulldown.
Uni-directional serial interface data in 4-pin mode (CONFIG5 sif4). The SDO pin is in high-impedance state
SDO
45
O
in 3-pin interface mode (default), but can optionally be used as a status output pin via CONFIG14
SDO_func_sel(2:0). Internal pulldown.
LVDS SYNC positive input data. The SYNCP/N LVDS pair has an internal 100
Ω termination resistor. By
SYNCP
5
I
default, the SYNCP/N input must be logic ‘1’ to enable a DAC analog output. See the LVDS SYNCP/N
Operation paragraph for a detailed description.
SYNCN
6
I
LVDS SYNC negative input data.
Digital supply voltage. (1.8 V) Connect to DVDD pins for normal operation. This supply pin is also used
VFUSE
44
I
for factory fuse programming.
6
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