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CDCM1804RGET Scheda tecnica(PDF) 4 Page - Texas Instruments

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Il numero della parte CDCM1804RGET
Spiegazioni elettronici  1:3 LVPECL CLOCK BUFFER ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER
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CDCM1804RGET Scheda tecnica(HTML) 4 Page - Texas Instruments

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RS0 = 0 Ω
EN
CDCM1804
S1
S0
RS1 = 60 kΩ
REN = Open
Setting for Mode 13:
EN = 1
S2 = VDD/2
S1 = VDD/2
S0 = 0
RS2 = 60 kΩ
S2
S0084-01
CDCM1804
SCAS697E – JULY 2003 – REVISED MAY 2005
Figure 1. Control Terminal Setting for Example
Table 1. Selection Mode Table
LVPECL(1)
LVCMOS
MODE
EN
S2
S1
S0
Y0
Y1
Y2
Y3
0
0
x
x
x
Off (high-z)
1
1
0
0
0
÷ 1
÷ 1
÷ 1
Off (high-z)
2
1
0
0
VDD/2
÷ 1
Off (high-z)
Off (high-z)
÷ 4
3
1
0
0
1
÷ 1
÷ 1
Off (high-z)
÷ 4
4
1
0
VDD/2
0
÷ 1
÷ 2
Off (high-z)
÷ 4
5
1
0
VDD/2
VDD/2
÷ 1
÷ 4
Off (high-z)
÷ 4
6
1
0
VDD/2
1
÷ 1
÷ 8
Off (high-z)
÷ 4
7
1
0
1
0
÷ 1
Off (high-z)
÷ 1
÷ 4
8
1
0
1
VDD/2
÷ 1
÷ 1
÷ 1
÷ 4
9
1
0
1
1
÷ 1
÷ 2
÷ 1
÷ 4
10
1
VDD/2
0
0
÷ 1
÷ 4
÷ 1
÷ 4
11
1
VDD/2
0
VDD/2
÷ 1
÷ 8
÷ 1
÷ 4
12
1
VDD/2
0
1
÷ 1
Off (high-z)
÷ 2
÷ 4
13
1
VDD/2
VDD/2
0
÷ 1
÷ 1
÷ 2
÷ 4
14
1
VDD/2
VDD/2
VDD/2
÷ 1
÷ 2
÷ 2
÷ 4
15
1
VDD/2
VDD/2
1
÷ 1
÷ 4
÷ 2
÷ 4
16
1
VDD/2
1
0
÷ 1
÷ 8
÷ 2
÷ 4
17
1
VDD/2
1
VDD/2
÷ 1
Off (high-z)
÷ 4
÷ 4
18
1
VDD/2
1
1
÷ 1
÷ 1
÷ 4
÷ 4
19
1
1
0
0
÷ 1
÷ 2
÷ 4
÷ 4
20
1
1
0
VDD/2
÷ 1
÷ 4
÷ 4
÷ 4
21
1
1
0
1
÷ 1
÷ 8
÷ 4
÷ 4
22
1
1
VDD/2
0
÷ 1
Off (high-z)
÷ 8
÷ 4
23
1
1
VDD/2
VDD/2
÷ 1
÷ 1
÷ 8
÷ 4
24
1
1
VDD/2
1
÷ 1
÷ 2
÷ 8
÷ 4
25
1
1
1
0
÷ 1
÷ 4
÷ 8
÷ 4
(1)
The LVPECL outputs are open-emitter stages. Thus, if you leave the unused LVPECL outputs Y0, Y1, or Y2 unconnected, then the
current consumption is minimized and noise impact to remaining outputs is neglectable. Also, each output can be individually disabled
by connecting the corresponding VDD input to GND.
4


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