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SI1865DDL Scheda tecnica(PDF) 8 Page - Vishay Siliconix |
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SI1865DDL Scheda tecnica(HTML) 8 Page - Vishay Siliconix |
8 / 10 page AN814 Vishay Siliconix www.vishay.com 2 Document Number: 71237 12-Dec-03 SC-70 (6-PIN) Room Ambient 25 _C Elevated Ambient 60 _C PD + TJ(max) * TA RqJA PD + 150oC * 25oC 400oC W PD + 312 mW PD + TJ(max) * TA RqJA PD + 150oC * 60oC 400oC W PD + 225 mW NOTE: Although they are intended for low-power applications, devices in the 6-pin SC-70 will handle power dissipation in excess of 0.2 W. Testing To aid comparison further, Figure 2 illustrates the dual-channel SC-70 thermal performance on two different board sizes and two different pad patterns. The results display the thermal performance out to steady state. The measured steady state values of RθJA for the dual 6-pin SC-70 are as follows: LITTLE FOOT SC-70 (6-PIN) 1) Minimum recommended pad pattern (see Figure 2) on the EVB of 0.5 inches x 0.6 inches. 518_C/W 2) Industry standard 1” square PCB with maximum copper both sides. 413_C/W Time (Secs) FIGURE 2. Comparison of Dual SC70-6 on EVB and 1” Square FR4 PCB. 0 1 500 100 200 100 1000 300 10 10-1 10-2 10-3 10-4 10-5 1” Square FR4 PCB Dual EVB 400 The results show that if the board area can be increased and maximum copper traces are added, the thermal resistance reduction is limited to 20%. This fact confirms that the power dissipation is restricted with the package size and the Alloy 42 leadframe. ASSOCIATED DOCUMENT Single-Channel LITTLE FOOT SC-70 6-Pin MOSFET Copper Leadframe Version, REcommended Pad Pattern and Thermal Performance, AN815, (http://www.vishay.com/doc?71334). |
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