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CDCVF25081 Scheda tecnica(PDF) 7 Page - Texas Instruments |
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CDCVF25081 Scheda tecnica(HTML) 7 Page - Texas Instruments |
7 / 12 page CDCVF25081 3.3-V PHASED-LOCK LOOP CLOCK DRIVER SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: ZO = 50 Ω, tr < 1.2 ns, tf < 1.2 ns. C. The outputs are measured one at a time with one transition per measurement. 1000 Ω From Output Under Test VDD 1000 Ω CL = 25 pF at f = 8 MHz to 100 MHz CL = 15 pF at f = 66 MHz to 200 MHz Figure 1. Test Load Circuit FBIN 50% VDD VOL VOH CLKIN 0 V VDD 50% VDD t(phoffset) Figure 2. Voltage Thresholds for Measurements, Phase Offset (PLL Mode) NOTE: odc = t1/(t1 + t2) x 100% 50% VDD Any Y Any Y tsk(0) 50% VDD tsk(0) 50% VDD t1 t2 Figure 3. Output Skew and Output Duty Cycle (PLL Mode) |
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