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ADC10831CIN Scheda tecnica(PDF) 7 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Il numero della parte ADC10831CIN
Spiegazioni elettronici  10-Bit Plus Sign Serial I/O A/D Converters with MUX, Sample/Hold and Reference
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Produttore elettronici  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC10831CIN Scheda tecnica(HTML) 7 Page - National Semiconductor (TI)

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Electrical Characteristics (Continued)
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur
Note 2
Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits For guaranteed specifcations and
test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance characteristics may
degrade when the device is not operated under the listed test conditions
Note 3
All voltages are measured with respect to GND unless otherwise specified
Note 4
When the input voltage (VIN) at any pin exceeds the power supplies (VIN k Vb or VIN l AVa or DVa) the current at that pln should be limited to 30 mA
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four
Note 5
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax iJA and the ambient temperature TA The maximum
allowable power dissipation at any temperature is PD e (TJmax b TA) iJA or the number given In the Absolute Maximum Ratings whichever is lower For this
device TJmax e 150 C The typical thermal resistance (iJA) of these Paris when board mounted can be found in the following table
Part Number
Thermal Resistance
Package Type
ADC10831CIN
82 CW
N16E
ADC10831CIWM
90 CW
M16B
ADC10832CIN
47 CW
N20A
ADC10832CIWM
80 CW
M20B
ADC10834CIN
47 CW
N20A
ADC10834CIWM
80 CW
M20B
ADC10838CIN
60 CW
N24A
ADC10838CIWM
75 CW
M24B
Note 6
The human body model is a 100 pF capacitor discharged through a 15 kX resistor into each pin The machine model is a 200 pF capacitor discharged
directly into each pin
Note 7
See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or the section titied ‘‘Surtace Mount’’ found in any post 1986 National
Semiconductor Linear Data Book for other methods of soldering surtace mount devices
Note 8
Two on-ohip diodes are tied to each analog input as shown below They will forward-conduct for analog input voltages one diode drop below Vb or one
diode drop greater than Va supply Be careful during testing at low Va and Vb levels (g45V) as high level analog inputs (g5V) can cause an input diode to
conduct especially at elevated temperatures which will cause errors In the conversion result The specification allows 50 mV forward bias of either diode this
means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV the output code will be oorrect Exceeding this range on an
unselected channel will corrupt the reading of a selected channel If AVa and DVa are minimum (45 VDC) and Vb is a maximum (b45 VDC) full scale must be
s g
455 VDC
TLH11391 – 6
Note 9
No connection exists between AVa and DVa on the chip
To guarantee accuracy it is required that the AVa and DVa be connected together to a power supply with separate bypass filter at eacn Va pin
Note 10
One LSB is referenced to 10 bits of resolution
Note 11
Typicals are at TJ e TA e 25 C and represent most likely pararmetric norm
Note 12
Tested limits are guaranteed to National’s AOQL (Average Outgolng Quality Level)
Note 13
Total unadjusted error includes offset full-scale linearity multiplexer and hold step errors
Note 14
The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together
Note 15
Channel leakage current is measured after the channel selection
Note 16
All the timing specifications are tested at the TTL logic levels VIL e 08V for a falling edge and VIH e 20V for a rising TRl-STATE voltage level is forced
to 14V
Note 17
The voltage applied to the digital inputs will affect the current drain during power down These devices are tested with CMOS logic levels (logic Low e 0V
and logic High e 5V) TTL levels increase the power down current to about 300 mA
7


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