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ADF4007BCP Scheda tecnica(PDF) 9 Page - Analog Devices |
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ADF4007BCP Scheda tecnica(HTML) 9 Page - Analog Devices |
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9 / 16 page  ADF4007 Rev. 0 | Page 9 of 16 THEORY OF OPERATION REFERENCE INPUT SECTION The reference input stage is shown in Figure 9. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. 100k Ω NC REFIN NC NO SW1 SW2 BUFFER SW3 TO R COUNTER POWER-DOWN CONTROL Figure 9. Reference Input Stage RF INPUT STAGE The RF input stage is shown in Figure 10 . It is followed by a 2-stage limiting amplifier to generate the CML clock levels needed for the prescaler. 500 Ω 1.6V 500 Ω AGND BIAS GENERATOR RFINA RFINB AVDD Figure 10. RF Input Stage PRESCALER P The prescaler, operating at CML levels, takes the clock from the RF input stage and divides it down to a manageable frequency for the PFD. The prescaler can be selected to be either 8, 16, 32, or 64, and is effectively the N value in the PLL synthesizer. The terms N and P are used interchangeably in this data sheet. N1 and N2 set the prescaler values. The prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 120 MHz, the maximum specified PFD frequency. Thus, with an RF frequency of 4 GHz, a prescaler value of 64 is valid, but a value of 32 or less is not valid. 2 ] [ REFIN VCO f N f × = R COUNTER The R counter is permanently set to 2. It allows the input reference frequency to be divided down by 2 to produce the reference clock to the phase frequency detector (PFD). PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The PFD takes inputs from the R counter and the N counter (prescaler, P) and produces an output proportional to the phase and frequency difference between them. Figure 11 is a simplified schematic. The PFD includes a fixed, 3 ns delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. LOGIC HI D1 D2 Q1 Q2 CLR1 CLR2 CP U1 U2 UP DOWN CPGND U3 R DIVIDER 3ns DELAY N DIVIDER VP CHARGE PUMP LOGIC HI Figure 11. PFD Simplified Schematic and Timing (In Lock) |
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