Motore di ricerca datesheet componenti elettronici |
|
SA25C512LMNX Scheda tecnica(PDF) 9 Page - List of Unclassifed Manufacturers |
|
SA25C512LMNX Scheda tecnica(HTML) 9 Page - List of Unclassifed Manufacturers |
9 / 19 page SA25C512 Data Sheet SAIFUN 9 Serial Interface Description Master The device that generates the SCK. Slave As the SCK pin is always an input, the SA25C512 always operates as a slave. Transmitter/Receiver The SA25C512 has separate pins designated for data transmission and reception. Serial Opcode The first byte is received after the device is selected. This byte contains the opcode that defines the operation to be performed (for more details, refer to Table 5, page 10). Invalid Opcode If an invalid opcode is received, no data is shifted into the SA25C512, and the serial output pin remains in a high impedance state until a CSb falling edge is detected again, which reinitializes the serial communication. Chip Select (CSb) The SA25C512 is selected when the CSb pin is low. When the device is not selected, data is not accepted via the SI pin, and the SO pin remains in a high impedance state. HOLDb The HOLDb pin is used in conjunction with the CSb pin to select the SA25C512. When the device is selected and a serial sequence is underway, HOLDb can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLDb pin must be brought low while the SCK pin is low. To resume serial communication, the HOLDb pin is brought high while the SCK pin is low (SCK may still toggle during HOLDb). Inputs to the SI pin are ignored while the SO pin is in the high impedance state. Write Protect The WPb pin enables write operations to the Status register when held high. When the WPb pin is brought low and the WPBEN bit is 1, all write operations to the status register are inhibited (for more details, refer to Table 8, page 11). If WPb goes low while CSb is still low, the write to the status register is interrupted. If the internal write cycle has already been initiated, WPb going low has no effect on any write operation to the status register. The WPb pin function is blocked when the WPBEN bit in the status register is 0, which enables the user to install the SA25F020 in a system with the WPb pin tied to ground but still able to write to the status register. All WPb pin functions are enabled when the WPBEN bit is set to 1. |
Codice articolo simile - SA25C512LMNX |
|
Descrizione simile - SA25C512LMNX |
|
|
Link URL |
Privacy Policy |
ALLDATASHEETIT.COM |
Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |