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MTV016 Scheda tecnica(PDF) 4 Page - List of Unclassifed Manufacturers |
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MTV016 Scheda tecnica(HTML) 4 Page - List of Unclassifed Manufacturers |
4 / 11 page MYSON TECHNOLOGY MTV016 MTV016 Revision 2.0 01/01/1999 4/11 There are 2 types of data that should be accessed through the serial data interface: ADDRESS bytes and ATTRIBUTE bytes. The protocol is the same for both except for bit 6 of the row address. The MSB (b7) bit is used to distinguish row and column addresses when transferring data from the external controller. Bit 6 of the row address is used to distinguish the ADDRESS byte when it is set to "0" and the ATTRIBUTE byte when it is set to "1", or to differentiate the column address for formats (a), (b) and (c), respectively. The configuration of transmission formats is shown in Table 1: Table 1. Configuration of Transmission Formats Address b7 b6 b5 b4 b3 b2 b1 b0 Format Row 1 0 x x R3 R2 R1 R0 a,b,c Columnab 0 0 x C4 C3 C2 C1 C0 a,b ADDRESS BYTES Columnc 0 1 x C4 C3 C2 C1 C0 c Row 1 1 x x R3 R2 R1 R0 a,b,c Columnab 0 0 x C4 C3 C2 C1 C0 a,b ATTRIBUTE BYTES Columnc 0 1 x C4 C3 C2 C1 C0 c Initiate ROW COL c COL ab DA c DA ab 1, X 0, 1 0, 1 1, X 1, X format (a) format (b) format (c) X, X 0, X Input = b7, b6 0, 0 Figure 4. Transmission State Diagram The data transmission is permitted to change from format (a) to formats (b) and (c), or from format (b) to format (a), but not from format (c) back to formats (a) and (b). The alternation between formats is configured as the state diagram shown in Figure 4. 3.2 Address Bus Administrator The administrator manages bus address arbitration of internal registers during external data writing. The external data, which is written to registers through the serial data interface, must be synchronized by internal display timing. In addition, the administrator also provides automatic incrementing to the address bus when external writing using format (c). 3.3 Vertical Display Control The vertical display control can generate different vertical display sizes for most display standards in current monitors. The vertical display size is calculated with the information of the double character height bit (CHS) and the vertical display height control register (CH6-CH0). The algorithm of repeating |
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